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History: v1..v2: - dropped device_type except for cpu & pci. I have the compatible string for pci so I can drop the device_type once it is possible - I lowercased all compatible types. I will need to resend some patches which have upper case intel - The cpu had the same compatible string as the soc node. So I added to the soc node -immr for internel memory mapped registers. - I added generic names for all parts. - I reworked the i2c bars matching the way you suggested. I added a compatible node for the PCI device which only the PCI ids in its compatible string. The bars (each represents a complete i2c controller) have a "intel,ce4100-i2c-controller" compatible node. It is not used by the driver. The driver is probed via PCI ids (by the pci subsystem not OF) and matches the bar address against the ressource in the child node. Once there is a hit the node is attached. - The SPI driver is also probed via pci. However I also attached a compatible property based on PCI ids v2..v3: - intel,ce4100-immr become intel,ce4100-cp. cp stands for core peripherals. The Atom data sheet talks here about ACPI devices. Since we don't have ACPI this does not apply here. - The interrupt map is gone. There are now plenty of device nodes. - The "unit address string" got fixed, it uses not DD,V format. v3..v4: - added descriptions for compatible nodes introduced here: - intel,ce4100-ioapic - intel,ce4100-lapic - intel,ce4100-hpet - intel,ce4100 - intel,ce4100-cp - intel,ce4100-pci - added a description about I2C controller magic. - Added gpio-controller and gpio-cells property to gpio devices. Those properties are not (yet) used. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
39 lines
1.2 KiB
Plaintext
39 lines
1.2 KiB
Plaintext
CE4100 Device Tree Bindings
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---------------------------
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The CE4100 SoC uses for in core peripherals the following compatible
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format: <vendor>,<chip>-<device>.
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Many of the "generic" devices like HPET or IO APIC have the ce4100
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name in their compatible property because they first appeared in this
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SoC.
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The CPU node
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------------
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,ce4100";
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reg = <0>;
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lapic = <&lapic0>;
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};
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The reg property describes the CPU number. The lapic property points to
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the local APIC timer.
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The SoC node
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------------
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This node describes the in-core peripherals. Required property:
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compatible = "intel,ce4100-cp";
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The PCI node
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------------
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This node describes the PCI bus on the SoC. Its property should be
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compatible = "intel,ce4100-pci", "pci";
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If the OS is using the IO-APIC for interrupt routing then the reported
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interrupt numbers for devices is no longer true. In order to obtain the
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correct interrupt number, the child node which represents the device has
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to contain the interrupt property. Besides the interrupt property it has
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to contain at least the reg property containing the PCI bus address and
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compatible property according to "PCI Bus Binding Revision 2.1".
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