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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7f47e1c52d
We don't need to share PVH GDT layout with other GDTs, especially since we now have a PVH-speciific entry (for stack canary segment). Define PVH's own selectors. (As a side effect of this change we are also fixing improper reference to __KERNEL_CS) Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Juergen Gross <jgross@suse.com> Signed-off-by: Juergen Gross <jgross@suse.com>
189 lines
4.6 KiB
ArmAsm
189 lines
4.6 KiB
ArmAsm
/*
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* Copyright C 2016, Oracle and/or its affiliates. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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.code32
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.text
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#define _pa(x) ((x) - __START_KERNEL_map)
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#include <linux/elfnote.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/asm.h>
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#include <asm/boot.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <xen/interface/elfnote.h>
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__HEAD
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/*
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* Entry point for PVH guests.
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*
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* Xen ABI specifies the following register state when we come here:
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*
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* - `ebx`: contains the physical memory address where the loader has placed
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* the boot start info structure.
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* - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
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* - `cr4`: all bits are cleared.
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* - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’
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* and a limit of ‘0xFFFFFFFF’. The selector value is unspecified.
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* - `ds`, `es`: must be a 32-bit read/write data segment with a base of
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* ‘0’ and a limit of ‘0xFFFFFFFF’. The selector values are all
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* unspecified.
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* - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
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* of '0x67'.
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* - `eflags`: bit 17 (VM) must be cleared. Bit 9 (IF) must be cleared.
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* Bit 8 (TF) must be cleared. Other bits are all unspecified.
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*
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* All other processor registers and flag bits are unspecified. The OS is in
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* charge of setting up it's own stack, GDT and IDT.
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*/
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#define PVH_GDT_ENTRY_CS 1
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#define PVH_GDT_ENTRY_DS 2
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#define PVH_GDT_ENTRY_CANARY 3
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#define PVH_CS_SEL (PVH_GDT_ENTRY_CS * 8)
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#define PVH_DS_SEL (PVH_GDT_ENTRY_DS * 8)
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#define PVH_CANARY_SEL (PVH_GDT_ENTRY_CANARY * 8)
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ENTRY(pvh_start_xen)
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cld
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lgdt (_pa(gdt))
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mov $PVH_DS_SEL,%eax
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mov %eax,%ds
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mov %eax,%es
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mov %eax,%ss
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/* Stash hvm_start_info. */
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mov $_pa(pvh_start_info), %edi
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mov %ebx, %esi
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mov _pa(pvh_start_info_sz), %ecx
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shr $2,%ecx
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rep
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movsl
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mov $_pa(early_stack_end), %esp
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/* Enable PAE mode. */
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mov %cr4, %eax
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orl $X86_CR4_PAE, %eax
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mov %eax, %cr4
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#ifdef CONFIG_X86_64
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/* Enable Long mode. */
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mov $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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/* Enable pre-constructed page tables. */
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mov $_pa(init_top_pgt), %eax
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mov %eax, %cr3
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mov $(X86_CR0_PG | X86_CR0_PE), %eax
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mov %eax, %cr0
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/* Jump to 64-bit mode. */
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ljmp $PVH_CS_SEL, $_pa(1f)
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/* 64-bit entry point. */
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.code64
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1:
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/* Set base address in stack canary descriptor. */
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mov $MSR_GS_BASE,%ecx
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mov $_pa(canary), %eax
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xor %edx, %edx
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wrmsr
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call xen_prepare_pvh
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/* startup_64 expects boot_params in %rsi. */
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mov $_pa(pvh_bootparams), %rsi
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mov $_pa(startup_64), %rax
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jmp *%rax
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#else /* CONFIG_X86_64 */
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/* Set base address in stack canary descriptor. */
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movl $_pa(gdt_start),%eax
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movl $_pa(canary),%ecx
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movw %cx, (PVH_GDT_ENTRY_CANARY * 8) + 2(%eax)
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shrl $16, %ecx
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movb %cl, (PVH_GDT_ENTRY_CANARY * 8) + 4(%eax)
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movb %ch, (PVH_GDT_ENTRY_CANARY * 8) + 7(%eax)
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mov $PVH_CANARY_SEL,%eax
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mov %eax,%gs
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call mk_early_pgtbl_32
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mov $_pa(initial_page_table), %eax
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mov %eax, %cr3
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mov %cr0, %eax
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or $(X86_CR0_PG | X86_CR0_PE), %eax
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mov %eax, %cr0
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ljmp $PVH_CS_SEL, $1f
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1:
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call xen_prepare_pvh
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mov $_pa(pvh_bootparams), %esi
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/* startup_32 doesn't expect paging and PAE to be on. */
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ljmp $PVH_CS_SEL, $_pa(2f)
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2:
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mov %cr0, %eax
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and $~X86_CR0_PG, %eax
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mov %eax, %cr0
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mov %cr4, %eax
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and $~X86_CR4_PAE, %eax
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mov %eax, %cr4
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ljmp $PVH_CS_SEL, $_pa(startup_32)
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#endif
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END(pvh_start_xen)
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.section ".init.data","aw"
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.balign 8
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gdt:
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.word gdt_end - gdt_start
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.long _pa(gdt_start)
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.word 0
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gdt_start:
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.quad 0x0000000000000000 /* NULL descriptor */
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#ifdef CONFIG_X86_64
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.quad GDT_ENTRY(0xa09a, 0, 0xfffff) /* PVH_CS_SEL */
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#else
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.quad GDT_ENTRY(0xc09a, 0, 0xfffff) /* PVH_CS_SEL */
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#endif
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.quad GDT_ENTRY(0xc092, 0, 0xfffff) /* PVH_DS_SEL */
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.quad GDT_ENTRY(0x4090, 0, 0x18) /* PVH_CANARY_SEL */
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gdt_end:
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.balign 16
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canary:
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.fill 48, 1, 0
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early_stack:
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.fill 256, 1, 0
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early_stack_end:
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ELFNOTE(Xen, XEN_ELFNOTE_PHYS32_ENTRY,
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_ASM_PTR (pvh_start_xen - __START_KERNEL_map))
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