mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
9dd660eb1c
Add r8a7795 IPMMU-PV1 and keep it disabled by default.
This device is not present in r8a7795 ES1.x and
is removed from the DT of those SoCs.
This corrects an omission in
3b7e7848f0 ("arm64: dts: renesas: r8a7795: Add IPMMU device nodes")
This does not have any runtime effect.
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
178 lines
3.9 KiB
Plaintext
178 lines
3.9 KiB
Plaintext
/*
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* Device Tree Source for the r8a7795 ES1.x SoC
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include "r8a7795.dtsi"
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&soc {
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xhci1: usb@ee040000 {
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compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
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reg = <0 0xee040000 0 0xc00>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 327>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 327>;
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status = "disabled";
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};
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/delete-node/ mmu@febe0000;
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/delete-node/ mmu@fe980000;
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/delete-node/ mmu@fd950000;
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/delete-node/ mmu@fd960000;
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/delete-node/ mmu@fd970000;
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ipmmu_mp1: mmu@ec680000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xec680000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 5>;
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#iommu-cells = <1>;
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};
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ipmmu_sy: mmu@e7730000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xe7730000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 8>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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/delete-node/ usb-phy@ee0e0200;
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/delete-node/ usb@ee0e0100;
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/delete-node/ usb@ee0e0000;
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/delete-node/ usb@e659c000;
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/delete-node/ dma-controller@e6460000;
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/delete-node/ dma-controller@e6470000;
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fcpf2: fcp@fe952000 {
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compatible = "renesas,fcpf";
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reg = <0 0xfe952000 0 0x200>;
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clocks = <&cpg CPG_MOD 613>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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resets = <&cpg 613>;
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iommus = <&ipmmu_vp0 2>;
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};
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vspi2: vsp@fe9c0000 {
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compatible = "renesas,vsp2";
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reg = <0 0xfe9c0000 0 0x8000>;
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interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 629>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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resets = <&cpg 629>;
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renesas,fcp = <&fcpvi2>;
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};
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fcpvi2: fcp@fe9cf000 {
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compatible = "renesas,fcpv";
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reg = <0 0xfe9cf000 0 0x200>;
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clocks = <&cpg CPG_MOD 609>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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resets = <&cpg 609>;
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iommus = <&ipmmu_vp0 10>;
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};
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vspd3: vsp@fea38000 {
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compatible = "renesas,vsp2";
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reg = <0 0xfea38000 0 0x8000>;
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interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 620>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 620>;
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renesas,fcp = <&fcpvd3>;
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};
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fcpvd3: fcp@fea3f000 {
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compatible = "renesas,fcpv";
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reg = <0 0xfea3f000 0 0x200>;
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clocks = <&cpg CPG_MOD 600>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 600>;
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iommus = <&ipmmu_vi0 11>;
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};
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fdp1@fe948000 {
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compatible = "renesas,fdp1";
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reg = <0 0xfe948000 0 0x2400>;
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interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 117>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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resets = <&cpg 117>;
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renesas,fcp = <&fcpf2>;
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};
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};
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&gpio1 {
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gpio-ranges = <&pfc 0 32 28>;
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};
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&ipmmu_vi0 {
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renesas,ipmmu-main = <&ipmmu_mm 11>;
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};
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&ipmmu_vp0 {
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renesas,ipmmu-main = <&ipmmu_mm 12>;
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};
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&ipmmu_vc0 {
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renesas,ipmmu-main = <&ipmmu_mm 9>;
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};
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&ipmmu_vc1 {
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renesas,ipmmu-main = <&ipmmu_mm 10>;
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};
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&ipmmu_rt {
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renesas,ipmmu-main = <&ipmmu_mm 7>;
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};
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&audma0 {
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iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
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<&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
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<&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
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<&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
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<&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
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<&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
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<&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
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<&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
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};
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&audma1 {
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iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
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<&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
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<&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
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<&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
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<&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
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<&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
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<&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
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<&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
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};
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&fcpvb1 {
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iommus = <&ipmmu_vp0 7>;
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};
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&fcpf1 {
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iommus = <&ipmmu_vp0 1>;
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};
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&fcpvi1 {
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iommus = <&ipmmu_vp0 9>;
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};
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&fcpvd2 {
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iommus = <&ipmmu_vi0 10>;
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};
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&du {
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vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
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};
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