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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d3be6d2a08
For platform_suspend_ops, the finish call is too late to re-enable wake irqs and we need re-enable wake irqs on wake call instead. Otherwise noirq resume for devices has already happened. And then dev_pm_disarm_wake_irq() has already disabled the dedicated wake irqs when the interrupt triggers and the wake irq is never handled. For devices that are already in PM runtime suspended state when we enter suspend this means that a possible wake irq will never trigger. And this can lead into a situation where a device has a pending padconf wake irq, and the device will stay unresponsive to any further wake irqs. This issue can be easily reproduced by setting serial console log level to zero, letting the serial console idle, and suspend the system from an ssh terminal. Then try to wake up the system by typing to the serial console. Note that this affects only omap3 PRM interrupt as that's currently the only omap variant that does anything in omap_pm_wake(). In general, for the wake irqs to work, the interrupt must have either IRQF_NO_SUSPEND or IRQF_EARLY_RESUME set for it to trigger before dev_pm_disarm_wake_irq() disables the wake irqs. Reported-by: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
257 lines
5.4 KiB
C
257 lines
5.4 KiB
C
/*
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* pm.c - Common OMAP2+ power management-related code
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/pm_opp.h>
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#include <linux/export.h>
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#include <linux/suspend.h>
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#include <linux/cpu.h>
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#include <asm/system_misc.h>
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#include "omap-pm.h"
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#include "omap_device.h"
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#include "common.h"
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#include "soc.h"
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#include "prcm-common.h"
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#include "voltage.h"
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#include "powerdomain.h"
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#include "clockdomain.h"
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#include "pm.h"
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#ifdef CONFIG_SUSPEND
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/*
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* omap_pm_suspend: points to a function that does the SoC-specific
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* suspend work
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*/
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static int (*omap_pm_suspend)(void);
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#endif
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#ifdef CONFIG_PM
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/**
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* struct omap2_oscillator - Describe the board main oscillator latencies
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* @startup_time: oscillator startup latency
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* @shutdown_time: oscillator shutdown latency
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*/
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struct omap2_oscillator {
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u32 startup_time;
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u32 shutdown_time;
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};
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static struct omap2_oscillator oscillator = {
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.startup_time = ULONG_MAX,
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.shutdown_time = ULONG_MAX,
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};
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void omap_pm_setup_oscillator(u32 tstart, u32 tshut)
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{
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oscillator.startup_time = tstart;
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oscillator.shutdown_time = tshut;
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}
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void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
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{
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if (!tstart || !tshut)
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return;
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*tstart = oscillator.startup_time;
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*tshut = oscillator.shutdown_time;
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}
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#endif
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int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
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{
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clkdm_allow_idle(clkdm);
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return 0;
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}
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/*
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* This API is to be called during init to set the various voltage
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* domains to the voltage as per the opp table. Typically we boot up
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* at the nominal voltage. So this function finds out the rate of
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* the clock associated with the voltage domain, finds out the correct
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* opp entry and sets the voltage domain to the voltage specified
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* in the opp entry
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*/
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static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
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const char *oh_name)
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{
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struct voltagedomain *voltdm;
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struct clk *clk;
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struct dev_pm_opp *opp;
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unsigned long freq, bootup_volt;
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struct device *dev;
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if (!vdd_name || !clk_name || !oh_name) {
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pr_err("%s: invalid parameters\n", __func__);
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goto exit;
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}
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if (!strncmp(oh_name, "mpu", 3))
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/*
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* All current OMAPs share voltage rail and clock
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* source, so CPU0 is used to represent the MPU-SS.
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*/
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dev = get_cpu_device(0);
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else
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dev = omap_device_get_by_hwmod_name(oh_name);
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if (IS_ERR(dev)) {
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pr_err("%s: Unable to get dev pointer for hwmod %s\n",
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__func__, oh_name);
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goto exit;
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}
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voltdm = voltdm_lookup(vdd_name);
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if (!voltdm) {
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pr_err("%s: unable to get vdd pointer for vdd_%s\n",
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__func__, vdd_name);
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goto exit;
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}
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clk = clk_get(NULL, clk_name);
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if (IS_ERR(clk)) {
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pr_err("%s: unable to get clk %s\n", __func__, clk_name);
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goto exit;
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}
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freq = clk_get_rate(clk);
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clk_put(clk);
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opp = dev_pm_opp_find_freq_ceil(dev, &freq);
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if (IS_ERR(opp)) {
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pr_err("%s: unable to find boot up OPP for vdd_%s\n",
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__func__, vdd_name);
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goto exit;
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}
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bootup_volt = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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if (!bootup_volt) {
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pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
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__func__, vdd_name);
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goto exit;
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}
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voltdm_scale(voltdm, bootup_volt);
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return 0;
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exit:
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pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
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return -EINVAL;
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}
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#ifdef CONFIG_SUSPEND
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static int omap_pm_enter(suspend_state_t suspend_state)
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{
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int ret = 0;
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if (!omap_pm_suspend)
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return -ENOENT; /* XXX doublecheck */
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switch (suspend_state) {
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case PM_SUSPEND_MEM:
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ret = omap_pm_suspend();
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int omap_pm_begin(suspend_state_t state)
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{
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cpu_idle_poll_ctrl(true);
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if (soc_is_omap34xx())
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omap_prcm_irq_prepare();
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return 0;
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}
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static void omap_pm_end(void)
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{
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cpu_idle_poll_ctrl(false);
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}
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static void omap_pm_wake(void)
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{
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if (soc_is_omap34xx())
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omap_prcm_irq_complete();
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}
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static const struct platform_suspend_ops omap_pm_ops = {
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.begin = omap_pm_begin,
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.end = omap_pm_end,
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.enter = omap_pm_enter,
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.wake = omap_pm_wake,
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.valid = suspend_valid_only_mem,
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};
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/**
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* omap_common_suspend_init - Set common suspend routines for OMAP SoCs
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* @pm_suspend: function pointer to SoC specific suspend function
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*/
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void omap_common_suspend_init(void *pm_suspend)
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{
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omap_pm_suspend = pm_suspend;
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suspend_set_ops(&omap_pm_ops);
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}
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#endif /* CONFIG_SUSPEND */
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static void __init omap3_init_voltages(void)
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{
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if (!soc_is_omap34xx())
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return;
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omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
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omap2_set_init_voltage("core", "l3_ick", "l3_main");
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}
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static void __init omap4_init_voltages(void)
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{
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if (!soc_is_omap44xx())
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return;
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omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
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omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
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omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
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}
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static int __init omap2_common_pm_init(void)
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{
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omap_pm_if_init();
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return 0;
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}
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omap_postcore_initcall(omap2_common_pm_init);
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int __init omap2_common_pm_late_init(void)
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{
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/* Init the voltage layer */
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omap3_twl_init();
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omap4_twl_init();
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omap_voltage_late_init();
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/* Initialize the voltages */
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omap3_init_voltages();
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omap4_init_voltages();
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/* Smartreflex device init */
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omap_devinit_smartreflex();
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return 0;
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}
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