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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 17:56:50 +07:00
187f1882b5
If a header file is making use of BUG, BUG_ON, BUILD_BUG_ON, or any other BUG variant in a static inline (i.e. not in a #define) then that header really should be including <linux/bug.h> and not just expecting it to be implicitly present. We can make this change risk-free, since if the files using these headers didn't have exposure to linux/bug.h already, they would have been causing compile failures/warnings. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
322 lines
8.6 KiB
C
322 lines
8.6 KiB
C
#ifndef __ASM_AVR32_IO_H
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#define __ASM_AVR32_IO_H
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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#include <mach/io.h>
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/* virt_to_phys will only work when address is in P1 or P2 */
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static __inline__ unsigned long virt_to_phys(volatile void *address)
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{
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return PHYSADDR(address);
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}
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static __inline__ void * phys_to_virt(unsigned long address)
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{
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return (void *)P1SEGADDR(address);
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}
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#define cached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
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#define uncached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
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#define phys_to_cached(addr) ((void *)P1SEGADDR(addr))
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#define phys_to_uncached(addr) ((void *)P2SEGADDR(addr))
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/*
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* Generic IO read/write. These perform native-endian accesses. Note
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* that some architectures will want to re-define __raw_{read,write}w.
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*/
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extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
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extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
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extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
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extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
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extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
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extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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static inline void __raw_writeb(u8 v, volatile void __iomem *addr)
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{
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*(volatile u8 __force *)addr = v;
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}
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static inline void __raw_writew(u16 v, volatile void __iomem *addr)
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{
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*(volatile u16 __force *)addr = v;
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}
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static inline void __raw_writel(u32 v, volatile void __iomem *addr)
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{
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*(volatile u32 __force *)addr = v;
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}
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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return *(const volatile u8 __force *)addr;
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}
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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return *(const volatile u16 __force *)addr;
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}
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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return *(const volatile u32 __force *)addr;
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}
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/* Convert I/O port address to virtual address */
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#ifndef __io
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# define __io(p) ((void *)phys_to_uncached(p))
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#endif
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/*
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* Not really sure about the best way to slow down I/O on
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* AVR32. Defining it as a no-op until we have an actual test case.
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*/
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#define SLOW_DOWN_IO do { } while (0)
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#define __BUILD_MEMORY_SINGLE(pfx, bwl, type) \
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static inline void \
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pfx##write##bwl(type val, volatile void __iomem *addr) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
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__val = pfx##ioswab##bwl(__addr, val); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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*__addr = __val; \
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} \
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\
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static inline type pfx##read##bwl(const volatile void __iomem *addr) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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__val = *__addr; \
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return pfx##ioswab##bwl(__addr, __val); \
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}
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#define __BUILD_IOPORT_SINGLE(pfx, bwl, type, p, slow) \
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static inline void pfx##out##bwl##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = __io(__swizzle_addr_##bwl(port)); \
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__val = pfx##ioswab##bwl(__addr, val); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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*__addr = __val; \
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slow; \
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} \
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\
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static inline type pfx##in##bwl##p(unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = __io(__swizzle_addr_##bwl(port)); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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__val = *__addr; \
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slow; \
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\
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return pfx##ioswab##bwl(__addr, __val); \
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}
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#define __BUILD_MEMORY_PFX(bus, bwl, type) \
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__BUILD_MEMORY_SINGLE(bus, bwl, type)
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#define BUILDIO_MEM(bwl, type) \
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__BUILD_MEMORY_PFX(, bwl, type) \
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__BUILD_MEMORY_PFX(__mem_, bwl, type)
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#define __BUILD_IOPORT_PFX(bus, bwl, type) \
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__BUILD_IOPORT_SINGLE(bus, bwl, type, ,) \
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__BUILD_IOPORT_SINGLE(bus, bwl, type, _p, SLOW_DOWN_IO)
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#define BUILDIO_IOPORT(bwl, type) \
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__BUILD_IOPORT_PFX(, bwl, type) \
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__BUILD_IOPORT_PFX(__mem_, bwl, type)
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BUILDIO_MEM(b, u8)
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BUILDIO_MEM(w, u16)
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BUILDIO_MEM(l, u32)
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BUILDIO_IOPORT(b, u8)
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BUILDIO_IOPORT(w, u16)
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BUILDIO_IOPORT(l, u32)
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define readb_be __raw_readb
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#define readw_be __raw_readw
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#define readl_be __raw_readl
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#define writeb_be __raw_writeb
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#define writew_be __raw_writew
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#define writel_be __raw_writel
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#define __BUILD_MEMORY_STRING(bwl, type) \
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static inline void writes##bwl(volatile void __iomem *addr, \
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const void *data, unsigned int count) \
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{ \
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const type *__data = data; \
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\
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while (count--) \
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__mem_write##bwl(*__data++, addr); \
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} \
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\
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static inline void reads##bwl(const volatile void __iomem *addr, \
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void *data, unsigned int count) \
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{ \
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type *__data = data; \
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\
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while (count--) \
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*__data++ = __mem_read##bwl(addr); \
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}
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#define __BUILD_IOPORT_STRING(bwl, type) \
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static inline void outs##bwl(unsigned long port, const void *data, \
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unsigned int count) \
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{ \
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const type *__data = data; \
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\
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while (count--) \
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__mem_out##bwl(*__data++, port); \
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} \
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\
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static inline void ins##bwl(unsigned long port, void *data, \
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unsigned int count) \
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{ \
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type *__data = data; \
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\
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while (count--) \
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*__data++ = __mem_in##bwl(port); \
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}
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#define BUILDSTRING(bwl, type) \
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__BUILD_MEMORY_STRING(bwl, type) \
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__BUILD_IOPORT_STRING(bwl, type)
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BUILDSTRING(b, u8)
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BUILDSTRING(w, u16)
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BUILDSTRING(l, u32)
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/*
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* io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
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*/
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#ifndef ioread8
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#define ioread8(p) ((unsigned int)readb(p))
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#define ioread16(p) ((unsigned int)readw(p))
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#define ioread16be(p) ((unsigned int)__raw_readw(p))
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#define ioread32(p) ((unsigned int)readl(p))
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#define ioread32be(p) ((unsigned int)__raw_readl(p))
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#define iowrite8(v,p) writeb(v, p)
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#define iowrite16(v,p) writew(v, p)
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#define iowrite16be(v,p) __raw_writew(v, p)
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#define iowrite32(v,p) writel(v, p)
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#define iowrite32be(v,p) __raw_writel(v, p)
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#define ioread8_rep(p,d,c) readsb(p,d,c)
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#define ioread16_rep(p,d,c) readsw(p,d,c)
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#define ioread32_rep(p,d,c) readsl(p,d,c)
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#define iowrite8_rep(p,s,c) writesb(p,s,c)
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#define iowrite16_rep(p,s,c) writesw(p,s,c)
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#define iowrite32_rep(p,s,c) writesl(p,s,c)
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#endif
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static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
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unsigned long count)
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{
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memcpy(to, (const void __force *)from, count);
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}
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static inline void memcpy_toio(volatile void __iomem *to, const void * from,
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unsigned long count)
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{
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memcpy((void __force *)to, from, count);
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}
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static inline void memset_io(volatile void __iomem *addr, unsigned char val,
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unsigned long count)
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{
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memset((void __force *)addr, val, count);
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}
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#define mmiowb()
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#define IO_SPACE_LIMIT 0xffffffff
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extern void __iomem *__ioremap(unsigned long offset, size_t size,
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unsigned long flags);
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extern void __iounmap(void __iomem *addr);
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/*
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* ioremap - map bus memory into CPU space
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* @offset bus address of the memory
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* @size size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to make
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* bus memory CPU accessible via the readb/.../writel functions and
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* the other mmio helpers. The returned address is not guaranteed to
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* be usable directly as a virtual address.
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*/
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#define ioremap(offset, size) \
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__ioremap((offset), (size), 0)
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#define ioremap_nocache(offset, size) \
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__ioremap((offset), (size), 0)
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#define iounmap(addr) \
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__iounmap(addr)
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#define cached(addr) P1SEGADDR(addr)
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#define uncached(addr) P2SEGADDR(addr)
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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#define page_to_bus page_to_phys
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#define bus_to_page phys_to_page
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/*
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* Create a virtual mapping cookie for an IO port range. There exists
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* no such thing as port-based I/O on AVR32, so a regular ioremap()
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* should do what we need.
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*/
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#define ioport_map(port, nr) ioremap(port, nr)
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#define ioport_unmap(port) iounmap(port)
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __ASM_AVR32_IO_H */
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