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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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098e51e517
Due to the additions of support for modes like AES-CCM and AES-GCM, which require large command tokens, the size of the descriptor has grown such that it now does not fit into the descriptor cache of a standard EIP97 anymore. This means that the driver no longer works on the Marvell Armada 3700LP chip (as used on e.g. Espressobin) that it has always supported. Additionally, performance on EIP197's like Marvell A8K may also degrade due to being able to fit less descriptors in the on-chip cache. Putting these tokens into the descriptor was really a hack and not how the design was supposed to be used - resource allocation did not account for it. So what this patch does, is move the command token out of the descriptor. To avoid having to allocate buffers on the fly for these command tokens, they are stuffed in a "shadow ring", which is a circular buffer of fixed size blocks that runs in lock-step with the descriptor ring. i.e. there is one token block per descriptor. The descriptor ring itself is then pre- populated with the pointers to these token blocks so these do not need to be filled in when building the descriptors later. Signed-off-by: Pascal van Leeuwen <pvanleeuwen@rambus.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
254 lines
6.5 KiB
C
254 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Marvell
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*
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include "safexcel.h"
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int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *cdr,
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struct safexcel_desc_ring *rdr)
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{
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int i;
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struct safexcel_command_desc *cdesc;
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dma_addr_t atok;
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/* Actual command descriptor ring */
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cdr->offset = priv->config.cd_offset;
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cdr->base = dmam_alloc_coherent(priv->dev,
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cdr->offset * EIP197_DEFAULT_RING_SIZE,
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&cdr->base_dma, GFP_KERNEL);
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if (!cdr->base)
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return -ENOMEM;
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cdr->write = cdr->base;
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cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
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cdr->read = cdr->base;
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/* Command descriptor shadow ring for storing additional token data */
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cdr->shoffset = priv->config.cdsh_offset;
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cdr->shbase = dmam_alloc_coherent(priv->dev,
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cdr->shoffset *
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EIP197_DEFAULT_RING_SIZE,
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&cdr->shbase_dma, GFP_KERNEL);
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if (!cdr->shbase)
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return -ENOMEM;
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cdr->shwrite = cdr->shbase;
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cdr->shbase_end = cdr->shbase + cdr->shoffset *
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(EIP197_DEFAULT_RING_SIZE - 1);
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/*
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* Populate command descriptors with physical pointers to shadow descs.
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* Note that we only need to do this once if we don't overwrite them.
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*/
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cdesc = cdr->base;
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atok = cdr->shbase_dma;
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for (i = 0; i < EIP197_DEFAULT_RING_SIZE; i++) {
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cdesc->atok_lo = lower_32_bits(atok);
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cdesc->atok_hi = upper_32_bits(atok);
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cdesc = (void *)cdesc + cdr->offset;
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atok += cdr->shoffset;
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}
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rdr->offset = priv->config.rd_offset;
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/* Use shoffset for result token offset here */
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rdr->shoffset = priv->config.res_offset;
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rdr->base = dmam_alloc_coherent(priv->dev,
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rdr->offset * EIP197_DEFAULT_RING_SIZE,
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&rdr->base_dma, GFP_KERNEL);
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if (!rdr->base)
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return -ENOMEM;
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rdr->write = rdr->base;
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rdr->base_end = rdr->base + rdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
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rdr->read = rdr->base;
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return 0;
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}
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inline int safexcel_select_ring(struct safexcel_crypto_priv *priv)
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{
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return (atomic_inc_return(&priv->ring_used) % priv->config.rings);
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}
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static void *safexcel_ring_next_cwptr(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *ring,
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bool first,
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struct safexcel_token **atoken)
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{
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void *ptr = ring->write;
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if (first)
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*atoken = ring->shwrite;
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if ((ring->write == ring->read - ring->offset) ||
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(ring->read == ring->base && ring->write == ring->base_end))
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return ERR_PTR(-ENOMEM);
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if (ring->write == ring->base_end) {
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ring->write = ring->base;
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ring->shwrite = ring->shbase;
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} else {
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ring->write += ring->offset;
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ring->shwrite += ring->shoffset;
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}
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return ptr;
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}
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static void *safexcel_ring_next_rwptr(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *ring,
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struct result_data_desc **rtoken)
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{
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void *ptr = ring->write;
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/* Result token at relative offset shoffset */
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*rtoken = ring->write + ring->shoffset;
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if ((ring->write == ring->read - ring->offset) ||
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(ring->read == ring->base && ring->write == ring->base_end))
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return ERR_PTR(-ENOMEM);
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if (ring->write == ring->base_end)
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ring->write = ring->base;
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else
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ring->write += ring->offset;
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return ptr;
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}
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void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *ring)
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{
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void *ptr = ring->read;
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if (ring->write == ring->read)
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return ERR_PTR(-ENOENT);
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if (ring->read == ring->base_end)
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ring->read = ring->base;
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else
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ring->read += ring->offset;
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return ptr;
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}
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inline void *safexcel_ring_curr_rptr(struct safexcel_crypto_priv *priv,
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int ring)
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{
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struct safexcel_desc_ring *rdr = &priv->ring[ring].rdr;
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return rdr->read;
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}
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inline int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
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int ring)
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{
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struct safexcel_desc_ring *rdr = &priv->ring[ring].rdr;
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return (rdr->read - rdr->base) / rdr->offset;
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}
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inline int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
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int ring,
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struct safexcel_result_desc *rdesc)
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{
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struct safexcel_desc_ring *rdr = &priv->ring[ring].rdr;
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return ((void *)rdesc - rdr->base) / rdr->offset;
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}
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void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *ring)
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{
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if (ring->write == ring->read)
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return;
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if (ring->write == ring->base) {
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ring->write = ring->base_end;
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ring->shwrite = ring->shbase_end;
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} else {
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ring->write -= ring->offset;
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ring->shwrite -= ring->shoffset;
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}
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}
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struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
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int ring_id,
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bool first, bool last,
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dma_addr_t data, u32 data_len,
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u32 full_data_len,
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dma_addr_t context,
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struct safexcel_token **atoken)
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{
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struct safexcel_command_desc *cdesc;
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cdesc = safexcel_ring_next_cwptr(priv, &priv->ring[ring_id].cdr,
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first, atoken);
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if (IS_ERR(cdesc))
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return cdesc;
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cdesc->particle_size = data_len;
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cdesc->rsvd0 = 0;
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cdesc->last_seg = last;
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cdesc->first_seg = first;
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cdesc->additional_cdata_size = 0;
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cdesc->rsvd1 = 0;
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cdesc->data_lo = lower_32_bits(data);
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cdesc->data_hi = upper_32_bits(data);
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if (first) {
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/*
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* Note that the length here MUST be >0 or else the EIP(1)97
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* may hang. Newer EIP197 firmware actually incorporates this
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* fix already, but that doesn't help the EIP97 and we may
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* also be running older firmware.
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*/
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cdesc->control_data.packet_length = full_data_len ?: 1;
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cdesc->control_data.options = EIP197_OPTION_MAGIC_VALUE |
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EIP197_OPTION_64BIT_CTX |
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EIP197_OPTION_CTX_CTRL_IN_CMD |
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EIP197_OPTION_RC_AUTO;
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cdesc->control_data.type = EIP197_TYPE_BCLA;
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cdesc->control_data.context_lo = lower_32_bits(context) |
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EIP197_CONTEXT_SMALL;
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cdesc->control_data.context_hi = upper_32_bits(context);
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}
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return cdesc;
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}
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struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
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int ring_id,
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bool first, bool last,
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dma_addr_t data, u32 len)
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{
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struct safexcel_result_desc *rdesc;
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struct result_data_desc *rtoken;
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rdesc = safexcel_ring_next_rwptr(priv, &priv->ring[ring_id].rdr,
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&rtoken);
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if (IS_ERR(rdesc))
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return rdesc;
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rdesc->particle_size = len;
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rdesc->rsvd0 = 0;
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rdesc->descriptor_overflow = 0;
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rdesc->buffer_overflow = 0;
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rdesc->last_seg = last;
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rdesc->first_seg = first;
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rdesc->result_size = EIP197_RD64_RESULT_SIZE;
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rdesc->rsvd1 = 0;
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rdesc->data_lo = lower_32_bits(data);
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rdesc->data_hi = upper_32_bits(data);
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/* Clear length & error code in result token */
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rtoken->packet_length = 0;
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rtoken->error_code = 0;
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return rdesc;
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}
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