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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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78aa09754d
Under certain conditions EMAC stop reception of incoming packets and
continuously increment R_MISS register instead of saving data into
provided buffer. The commit implement workaround for such situation.
Then the stall detected EMAC will be restarted.
On device the stall looks like the device lost it's dynamic IP address.
ifconfig shows that interface error counter rapidly increments.
At the same time on the DHCP server we can see continues DHCP-requests
from device.
In real network stalls happen really rarely. To make them frequent the
broadcast storm[1] should be simulated. For simulation it is necessary
to make following connections:
1. connect radxarock to 1st port of switch
2. connect some PC to 2nd port of switch
3. connect two other free ports together using standard ethernet cable,
in order to make a switching loop.
After that, is necessary to make a broadcast storm. For example, running on
PC 'ping' to some IP address triggers ARP-request storm. After some
time (~10sec), EMAC on rk3188 will stall.
Observed and tested on rk3188 radxarock.
[1] https://en.wikipedia.org/wiki/Broadcast_radiation
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
227 lines
6.2 KiB
C
227 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
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*
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* Registers and bits definitions of ARC EMAC
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*/
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#ifndef ARC_EMAC_H
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#define ARC_EMAC_H
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <linux/clk.h>
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/* STATUS and ENABLE Register bit masks */
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#define TXINT_MASK (1 << 0) /* Transmit interrupt */
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#define RXINT_MASK (1 << 1) /* Receive interrupt */
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#define ERR_MASK (1 << 2) /* Error interrupt */
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#define TXCH_MASK (1 << 3) /* Transmit chaining error interrupt */
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#define MSER_MASK (1 << 4) /* Missed packet counter error */
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#define RXCR_MASK (1 << 8) /* RXCRCERR counter rolled over */
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#define RXFR_MASK (1 << 9) /* RXFRAMEERR counter rolled over */
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#define RXFL_MASK (1 << 10) /* RXOFLOWERR counter rolled over */
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#define MDIO_MASK (1 << 12) /* MDIO complete interrupt */
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#define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
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/* CONTROL Register bit masks */
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#define EN_MASK (1 << 0) /* VMAC enable */
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#define TXRN_MASK (1 << 3) /* TX enable */
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#define RXRN_MASK (1 << 4) /* RX enable */
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#define DSBC_MASK (1 << 8) /* Disable receive broadcast */
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#define ENFL_MASK (1 << 10) /* Enable Full-duplex */
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#define PROM_MASK (1 << 11) /* Promiscuous mode */
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/* Buffer descriptor INFO bit masks */
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#define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
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#define FIRST_MASK (1 << 16) /* First buffer in chain */
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#define LAST_MASK (1 << 17) /* Last buffer in chain */
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#define LEN_MASK 0x000007FF /* last 11 bits */
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#define CRLS (1 << 21)
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#define DEFR (1 << 22)
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#define DROP (1 << 23)
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#define RTRY (1 << 24)
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#define LTCL (1 << 28)
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#define UFLO (1 << 29)
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#define FOR_EMAC OWN_MASK
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#define FOR_CPU 0
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/* ARC EMAC register set combines entries for MAC and MDIO */
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enum {
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R_ID = 0,
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R_STATUS,
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R_ENABLE,
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R_CTRL,
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R_POLLRATE,
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R_RXERR,
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R_MISS,
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R_TX_RING,
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R_RX_RING,
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R_ADDRL,
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R_ADDRH,
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R_LAFL,
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R_LAFH,
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R_MDIO,
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};
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#define TX_TIMEOUT (400 * HZ / 1000) /* Transmission timeout */
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#define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
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#define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
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/**
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* struct arc_emac_bd - EMAC buffer descriptor (BD).
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*
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* @info: Contains status information on the buffer itself.
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* @data: 32-bit byte addressable pointer to the packet data.
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*/
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struct arc_emac_bd {
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__le32 info;
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dma_addr_t data;
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};
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/* Number of Rx/Tx BD's */
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#define RX_BD_NUM 128
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#define TX_BD_NUM 128
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#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
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#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
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/**
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* struct buffer_state - Stores Rx/Tx buffer state.
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* @sk_buff: Pointer to socket buffer.
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* @addr: Start address of DMA-mapped memory region.
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* @len: Length of DMA-mapped memory region.
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*/
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struct buffer_state {
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struct sk_buff *skb;
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DEFINE_DMA_UNMAP_ADDR(addr);
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DEFINE_DMA_UNMAP_LEN(len);
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};
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struct arc_emac_mdio_bus_data {
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struct gpio_desc *reset_gpio;
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int msec;
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};
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/**
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* struct arc_emac_priv - Storage of EMAC's private information.
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* @dev: Pointer to the current device.
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* @phy_dev: Pointer to attached PHY device.
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* @bus: Pointer to the current MII bus.
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* @regs: Base address of EMAC memory-mapped control registers.
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* @napi: Structure for NAPI.
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* @rxbd: Pointer to Rx BD ring.
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* @txbd: Pointer to Tx BD ring.
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* @rxbd_dma: DMA handle for Rx BD ring.
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* @txbd_dma: DMA handle for Tx BD ring.
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* @rx_buff: Storage for Rx buffers states.
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* @tx_buff: Storage for Tx buffers states.
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* @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
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* @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
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* @last_rx_bd: Index of the last Rx BD we've got from EMAC.
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* @link: PHY's last seen link state.
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* @duplex: PHY's last set duplex mode.
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* @speed: PHY's last set speed.
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*/
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struct arc_emac_priv {
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const char *drv_name;
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const char *drv_version;
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void (*set_mac_speed)(void *priv, unsigned int speed);
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/* Devices */
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struct device *dev;
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struct mii_bus *bus;
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struct arc_emac_mdio_bus_data bus_data;
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void __iomem *regs;
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struct clk *clk;
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struct napi_struct napi;
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struct arc_emac_bd *rxbd;
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struct arc_emac_bd *txbd;
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dma_addr_t rxbd_dma;
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dma_addr_t txbd_dma;
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struct buffer_state rx_buff[RX_BD_NUM];
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struct buffer_state tx_buff[TX_BD_NUM];
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unsigned int txbd_curr;
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unsigned int txbd_dirty;
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unsigned int last_rx_bd;
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unsigned int link;
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unsigned int duplex;
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unsigned int speed;
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unsigned int rx_missed_errors;
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};
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/**
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* arc_reg_set - Sets EMAC register with provided value.
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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* @value: Value to set in register.
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*/
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static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
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{
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iowrite32(value, priv->regs + reg * sizeof(int));
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}
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/**
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* arc_reg_get - Gets value of specified EMAC register.
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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*
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* returns: Value of requested register.
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*/
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static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
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{
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return ioread32(priv->regs + reg * sizeof(int));
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}
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/**
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* arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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* @mask: Mask to apply to specified register.
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*
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* This function reads initial register value, then applies provided mask
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* to it and then writes register back.
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*/
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static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
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{
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unsigned int value = arc_reg_get(priv, reg);
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arc_reg_set(priv, reg, value | mask);
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}
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/**
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* arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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* @mask: Mask to apply to specified register.
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*
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* This function reads initial register value, then applies provided mask
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* to it and then writes register back.
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*/
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static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
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{
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unsigned int value = arc_reg_get(priv, reg);
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arc_reg_set(priv, reg, value & ~mask);
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}
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int arc_mdio_probe(struct arc_emac_priv *priv);
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int arc_mdio_remove(struct arc_emac_priv *priv);
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int arc_emac_probe(struct net_device *ndev, int interface);
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int arc_emac_remove(struct net_device *ndev);
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#endif /* ARC_EMAC_H */
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