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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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169ca4b389
DE3 VI layers support alpha blending, but DE2 VI layers do not.
Additionally, DE3 VI layers support 10-bit RGB and YUV formats.
Make a separate list for DE3.
Fixes: c50519e6db ("drm/sun4i: Add basic support for DE3")
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20200224173901.174016-3-jernej.skrabec@siol.net
215 lines
6.9 KiB
C
215 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#ifndef _SUN8I_MIXER_H_
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#define _SUN8I_MIXER_H_
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "sun8i_csc.h"
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#include "sunxi_engine.h"
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#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
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#define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
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#define SUN8I_MIXER_GLOBAL_CTL 0x0
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#define SUN8I_MIXER_GLOBAL_STATUS 0x4
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#define SUN8I_MIXER_GLOBAL_DBUFF 0x8
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#define SUN8I_MIXER_GLOBAL_SIZE 0xc
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#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
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#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
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#define DE2_MIXER_UNIT_SIZE 0x6000
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#define DE3_MIXER_UNIT_SIZE 0x3000
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#define DE2_BLD_BASE 0x1000
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#define DE2_CH_BASE 0x2000
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#define DE2_CH_SIZE 0x1000
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#define DE3_BLD_BASE 0x0800
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#define DE3_CH_BASE 0x1000
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#define DE3_CH_SIZE 0x0800
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#define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
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#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
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#define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
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#define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
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#define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80)
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#define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
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#define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88)
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#define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c)
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#define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0)
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#define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4)
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#define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
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#define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100)
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#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
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((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y))
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#define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \
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((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c)
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#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
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#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
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#define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
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/* colors are always in AARRGGBB format */
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#define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
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/* The following numbers are some still unknown magic numbers */
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#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
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#define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
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#define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2)
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#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
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#define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch)
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#define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) | ((c) & 0xffff))
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#define SUN8I_MIXER_FBFMT_ARGB8888 0
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#define SUN8I_MIXER_FBFMT_ABGR8888 1
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#define SUN8I_MIXER_FBFMT_RGBA8888 2
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#define SUN8I_MIXER_FBFMT_BGRA8888 3
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#define SUN8I_MIXER_FBFMT_XRGB8888 4
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#define SUN8I_MIXER_FBFMT_XBGR8888 5
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#define SUN8I_MIXER_FBFMT_RGBX8888 6
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#define SUN8I_MIXER_FBFMT_BGRX8888 7
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#define SUN8I_MIXER_FBFMT_RGB888 8
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#define SUN8I_MIXER_FBFMT_BGR888 9
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#define SUN8I_MIXER_FBFMT_RGB565 10
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#define SUN8I_MIXER_FBFMT_BGR565 11
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#define SUN8I_MIXER_FBFMT_ARGB4444 12
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#define SUN8I_MIXER_FBFMT_ABGR4444 13
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#define SUN8I_MIXER_FBFMT_RGBA4444 14
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#define SUN8I_MIXER_FBFMT_BGRA4444 15
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#define SUN8I_MIXER_FBFMT_ARGB1555 16
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#define SUN8I_MIXER_FBFMT_ABGR1555 17
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#define SUN8I_MIXER_FBFMT_RGBA5551 18
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#define SUN8I_MIXER_FBFMT_BGRA5551 19
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#define SUN8I_MIXER_FBFMT_ARGB2101010 20
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#define SUN8I_MIXER_FBFMT_ABGR2101010 21
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#define SUN8I_MIXER_FBFMT_RGBA1010102 22
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#define SUN8I_MIXER_FBFMT_BGRA1010102 23
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#define SUN8I_MIXER_FBFMT_YUYV 0
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#define SUN8I_MIXER_FBFMT_UYVY 1
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#define SUN8I_MIXER_FBFMT_YVYU 2
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#define SUN8I_MIXER_FBFMT_VYUY 3
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#define SUN8I_MIXER_FBFMT_NV16 4
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#define SUN8I_MIXER_FBFMT_NV61 5
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#define SUN8I_MIXER_FBFMT_YUV422 6
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/* format 7 doesn't exist */
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#define SUN8I_MIXER_FBFMT_NV12 8
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#define SUN8I_MIXER_FBFMT_NV21 9
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#define SUN8I_MIXER_FBFMT_YUV420 10
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/* format 11 doesn't exist */
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/* format 12 is semi-planar YUV411 UVUV */
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/* format 13 is semi-planar YUV411 VUVU */
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#define SUN8I_MIXER_FBFMT_YUV411 14
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/* format 15 doesn't exist */
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/* format 16 is P010 YVU */
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#define SUN8I_MIXER_FBFMT_P010_YUV 17
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/* format 18 is P210 YVU */
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#define SUN8I_MIXER_FBFMT_P210_YUV 19
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/* format 20 is packed YVU444 10-bit */
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/* format 21 is packed YUV444 10-bit */
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/*
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* Sub-engines listed bellow are unused for now. The EN registers are here only
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* to be used to disable these sub-engines.
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*/
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#define SUN8I_MIXER_FCE_EN 0xa0000
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#define SUN8I_MIXER_BWS_EN 0xa2000
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#define SUN8I_MIXER_LTI_EN 0xa4000
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#define SUN8I_MIXER_PEAK_EN 0xa6000
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#define SUN8I_MIXER_ASE_EN 0xa8000
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#define SUN8I_MIXER_FCC_EN 0xaa000
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#define SUN8I_MIXER_DCSC_EN 0xb0000
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#define SUN50I_MIXER_FCE_EN 0x70000
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#define SUN50I_MIXER_PEAK_EN 0x70800
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#define SUN50I_MIXER_LCTI_EN 0x71000
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#define SUN50I_MIXER_BLS_EN 0x71800
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#define SUN50I_MIXER_FCC_EN 0x72000
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#define SUN50I_MIXER_DNS_EN 0x80000
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#define SUN50I_MIXER_DRC_EN 0xa0000
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#define SUN50I_MIXER_FMT_EN 0xa8000
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#define SUN50I_MIXER_CDC0_EN 0xd0000
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#define SUN50I_MIXER_CDC1_EN 0xd8000
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struct de2_fmt_info {
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u32 drm_fmt;
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u32 de2_fmt;
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bool rgb;
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enum sun8i_csc_mode csc;
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};
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/**
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* struct sun8i_mixer_cfg - mixer HW configuration
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* @vi_num: number of VI channels
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* @ui_num: number of UI channels
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* @scaler_mask: bitmask which tells which channel supports scaling
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* First, scaler supports for VI channels is defined and after that, scaler
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* support for UI channels. For example, if mixer has 2 VI channels without
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* scaler and 2 UI channels with scaler, bitmask would be 0xC.
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* @ccsc: select set of CCSC base addresses
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* Set value to 0 if this is first mixer or second mixer with VEP support.
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* Set value to 1 if this is second mixer without VEP support. Other values
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* are invalid.
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* @mod_rate: module clock rate that needs to be set in order to have
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* a functional block.
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* @is_de3: true, if this is next gen display engine 3.0, false otherwise.
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* @scaline_yuv: size of a scanline for VI scaler for YUV formats.
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*/
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struct sun8i_mixer_cfg {
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int vi_num;
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int ui_num;
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int scaler_mask;
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int ccsc;
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unsigned long mod_rate;
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unsigned int is_de3 : 1;
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unsigned int scanline_yuv;
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};
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struct sun8i_mixer {
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struct sunxi_engine engine;
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const struct sun8i_mixer_cfg *cfg;
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struct reset_control *reset;
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struct clk *bus_clk;
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struct clk *mod_clk;
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};
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static inline struct sun8i_mixer *
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engine_to_sun8i_mixer(struct sunxi_engine *engine)
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{
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return container_of(engine, struct sun8i_mixer, engine);
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}
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static inline u32
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sun8i_blender_base(struct sun8i_mixer *mixer)
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{
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return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
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}
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static inline u32
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sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
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{
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if (mixer->cfg->is_de3)
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return DE3_CH_BASE + channel * DE3_CH_SIZE;
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else
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return DE2_CH_BASE + channel * DE2_CH_SIZE;
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}
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const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
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#endif /* _SUN8I_MIXER_H_ */
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