mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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65156f2b1d
Initialize Monitor Mode Control Register 3 (MMCR3) SPR which is new in power10. For PowerISA v3.1, BHRB disable is controlled via Monitor Mode Control Register A (MMCRA) bit, namely "BHRB Recording Disable (BHRBRD)". This patch also initializes MMCRA BHRBRD to disable BHRB feature at boot for power10. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Reviewed-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1595489557-2047-1-git-send-email-atrajeev@linux.vnet.ibm.com
253 lines
4.7 KiB
ArmAsm
253 lines
4.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains low level CPU setup functions.
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/book3s/64/mmu-hash.h>
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/* Entry: r3 = crap, r4 = ptr to cputable entry
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*
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* Note that we can be called twice for pseudo-PVRs
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*/
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_GLOBAL(__setup_cpu_power7)
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mflr r11
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bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
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bl __init_LPCR_ISA206
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power7)
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mflr r11
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mfmsr r3
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rldicl. r0,r3,4,63
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
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bl __init_LPCR_ISA206
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mtlr r11
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blr
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_GLOBAL(__setup_cpu_power8)
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mflr r11
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bl __init_FSCR
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bl __init_PMU
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bl __init_PMU_ISA207
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bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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ori r3, r3, LPCR_PECEDH
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA206
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bl __init_HFSCR
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bl __init_PMU_HV
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bl __init_PMU_HV_ISA207
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power8)
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mflr r11
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bl __init_FSCR
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bl __init_PMU
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bl __init_PMU_ISA207
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mfmsr r3
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rldicl. r0,r3,4,63
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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ori r3, r3, LPCR_PECEDH
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA206
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bl __init_HFSCR
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bl __init_PMU_HV
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bl __init_PMU_HV_ISA207
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mtlr r11
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blr
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_GLOBAL(__setup_cpu_power10)
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mflr r11
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bl __init_FSCR_power10
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bl __init_PMU
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bl __init_PMU_ISA31
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b 1f
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_GLOBAL(__setup_cpu_power9)
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mflr r11
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bl __init_FSCR_power9
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bl __init_PMU
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1: bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_PSSCR,r0
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mtspr SPRN_LPID,r0
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mtspr SPRN_PID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
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or r3, r3, r4
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LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
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andc r3, r3, r4
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA300
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bl __init_HFSCR
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bl __init_PMU_HV
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power10)
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mflr r11
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bl __init_FSCR_power10
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bl __init_PMU
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bl __init_PMU_ISA31
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b 1f
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_GLOBAL(__restore_cpu_power9)
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mflr r11
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bl __init_FSCR_power9
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bl __init_PMU
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1: mfmsr r3
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rldicl. r0,r3,4,63
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_PSSCR,r0
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mtspr SPRN_LPID,r0
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mtspr SPRN_PID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
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or r3, r3, r4
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LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
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andc r3, r3, r4
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA300
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bl __init_HFSCR
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bl __init_PMU_HV
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mtlr r11
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blr
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__init_hvmode_206:
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/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
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mfmsr r3
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rldicl. r0,r3,4,63
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bnelr
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ld r5,CPU_SPEC_FEATURES(r4)
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LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
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andc r5,r5,r6
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std r5,CPU_SPEC_FEATURES(r4)
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blr
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__init_LPCR_ISA206:
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/* Setup a sane LPCR:
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* Called with initial LPCR in R3 and desired LPES 2-bit value in R4
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*
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* LPES = 0b01 (HSRR0/1 used for 0x500)
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* PECE = 0b111
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* DPFD = 4
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* HDICE = 0
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* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
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* VRMASD = 0b10000 (L=1, LP=00)
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*
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* Other bits untouched for now
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*/
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li r5,0x10
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rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
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/* POWER9 has no VRMASD */
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__init_LPCR_ISA300:
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rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
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ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
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li r5,4
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rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
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clrrdi r3,r3,1 /* clear HDICE */
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li r5,4
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rldimi r3,r5, LPCR_VC_SH, 0
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mtspr SPRN_LPCR,r3
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isync
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blr
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__init_FSCR_power10:
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mfspr r3, SPRN_FSCR
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ori r3, r3, FSCR_PREFIX
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mtspr SPRN_FSCR, r3
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// fall through
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__init_FSCR_power9:
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mfspr r3, SPRN_FSCR
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ori r3, r3, FSCR_SCV
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mtspr SPRN_FSCR, r3
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// fall through
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__init_FSCR:
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mfspr r3,SPRN_FSCR
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ori r3,r3,FSCR_TAR|FSCR_EBB
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mtspr SPRN_FSCR,r3
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blr
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__init_HFSCR:
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mfspr r3,SPRN_HFSCR
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ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
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HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
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mtspr SPRN_HFSCR,r3
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blr
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__init_PMU_HV:
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li r5,0
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mtspr SPRN_MMCRC,r5
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blr
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__init_PMU_HV_ISA207:
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li r5,0
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mtspr SPRN_MMCRH,r5
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blr
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__init_PMU:
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li r5,0
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mtspr SPRN_MMCRA,r5
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mtspr SPRN_MMCR0,r5
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mtspr SPRN_MMCR1,r5
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mtspr SPRN_MMCR2,r5
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blr
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__init_PMU_ISA207:
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li r5,0
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mtspr SPRN_MMCRS,r5
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blr
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__init_PMU_ISA31:
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li r5,0
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mtspr SPRN_MMCR3,r5
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LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
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mtspr SPRN_MMCRA,r5
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blr
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