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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3aa3e8407a
Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Sekhar Nori <nsekhar@ti.com>
112 lines
2.7 KiB
C
112 lines
2.7 KiB
C
/*
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* Header for code common to all DaVinci machines.
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
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#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
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#include <linux/compiler.h>
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#include <linux/types.h>
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struct sys_timer;
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extern struct sys_timer davinci_timer;
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extern void davinci_irq_init(void);
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extern void __iomem *davinci_intc_base;
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extern int davinci_intc_type;
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struct davinci_timer_instance {
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u32 base;
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u32 bottom_irq;
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u32 top_irq;
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unsigned long cmp_off;
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unsigned int cmp_irq;
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};
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struct davinci_timer_info {
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struct davinci_timer_instance *timers;
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unsigned int clockevent_id;
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unsigned int clocksource_id;
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};
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struct davinci_gpio_controller;
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/*
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* SoC info passed into common davinci modules.
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*
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* Base addresses in this structure should be physical and not virtual.
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* Modules that take such base addresses, should internally ioremap() them to
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* use.
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*/
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struct davinci_soc_info {
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struct map_desc *io_desc;
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unsigned long io_desc_num;
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u32 cpu_id;
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u32 jtag_id;
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u32 jtag_id_reg;
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struct davinci_id *ids;
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unsigned long ids_num;
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struct clk_lookup *cpu_clks;
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u32 *psc_bases;
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unsigned long psc_bases_num;
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u32 pinmux_base;
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const struct mux_config *pinmux_pins;
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unsigned long pinmux_pins_num;
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u32 intc_base;
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int intc_type;
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u8 *intc_irq_prios;
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unsigned long intc_irq_num;
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u32 *intc_host_map;
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struct davinci_timer_info *timer_info;
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int gpio_type;
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u32 gpio_base;
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unsigned gpio_num;
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unsigned gpio_irq;
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unsigned gpio_unbanked;
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struct davinci_gpio_controller *gpio_ctlrs;
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int gpio_ctlrs_num;
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struct platform_device *serial_dev;
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struct emac_platform_data *emac_pdata;
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dma_addr_t sram_dma;
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unsigned sram_len;
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};
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extern struct davinci_soc_info davinci_soc_info;
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extern void davinci_common_init(struct davinci_soc_info *soc_info);
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extern void davinci_init_ide(void);
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void davinci_restart(char mode, const char *cmd);
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void davinci_init_late(void);
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#ifdef CONFIG_DAVINCI_RESET_CLOCKS
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int davinci_clk_disable_unused(void);
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#else
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static inline int davinci_clk_disable_unused(void) { return 0; }
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#endif
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#ifdef CONFIG_CPU_FREQ
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int davinci_cpufreq_init(void);
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#else
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static inline int davinci_cpufreq_init(void) { return 0; }
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#endif
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#ifdef CONFIG_SUSPEND
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int davinci_pm_init(void);
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#else
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static inline int davinci_pm_init(void) { return 0; }
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#endif
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/* standard place to map on-chip SRAMs; they *may* support DMA */
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#define SRAM_VIRT 0xfffe0000
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#define SRAM_SIZE SZ_128K
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#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
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