mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-07 15:06:40 +07:00
a20d5fa61c
Signed-off-by: Eric Anholt <eric@anholt.net>
879 lines
25 KiB
C
879 lines
25 KiB
C
/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/**
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* DOC: Shader validator for VC4.
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*
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* The VC4 has no IOMMU between it and system memory, so a user with
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* access to execute shaders could escalate privilege by overwriting
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* system memory (using the VPM write address register in the
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* general-purpose DMA mode) or reading system memory it shouldn't
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* (reading it as a texture, or uniform data, or vertex data).
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*
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* This walks over a shader BO, ensuring that its accesses are
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* appropriately bounded, and recording how many texture accesses are
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* made and where so that we can do relocations for them in the
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* uniform stream.
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*/
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#include "vc4_drv.h"
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#include "vc4_qpu_defines.h"
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#define LIVE_REG_COUNT (32 + 32 + 4)
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struct vc4_shader_validation_state {
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/* Current IP being validated. */
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uint32_t ip;
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/* IP at the end of the BO, do not read shader[max_ip] */
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uint32_t max_ip;
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uint64_t *shader;
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struct vc4_texture_sample_info tmu_setup[2];
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int tmu_write_count[2];
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/* For registers that were last written to by a MIN instruction with
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* one argument being a uniform, the address of the uniform.
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* Otherwise, ~0.
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*
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* This is used for the validation of direct address memory reads.
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*/
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uint32_t live_min_clamp_offsets[LIVE_REG_COUNT];
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bool live_max_clamp_regs[LIVE_REG_COUNT];
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uint32_t live_immediates[LIVE_REG_COUNT];
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/* Bitfield of which IPs are used as branch targets.
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*
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* Used for validation that the uniform stream is updated at the right
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* points and clearing the texturing/clamping state.
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*/
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unsigned long *branch_targets;
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/* Set when entering a basic block, and cleared when the uniform
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* address update is found. This is used to make sure that we don't
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* read uniforms when the address is undefined.
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*/
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bool needs_uniform_address_update;
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/* Set when we find a backwards branch. If the branch is backwards,
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* the taraget is probably doing an address reset to read uniforms,
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* and so we need to be sure that a uniforms address is present in the
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* stream, even if the shader didn't need to read uniforms in later
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* basic blocks.
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*/
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bool needs_uniform_address_for_loop;
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};
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static uint32_t
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waddr_to_live_reg_index(uint32_t waddr, bool is_b)
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{
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if (waddr < 32) {
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if (is_b)
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return 32 + waddr;
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else
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return waddr;
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} else if (waddr <= QPU_W_ACC3) {
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return 64 + waddr - QPU_W_ACC0;
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} else {
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return ~0;
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}
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}
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static uint32_t
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raddr_add_a_to_live_reg_index(uint64_t inst)
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{
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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if (add_a == QPU_MUX_A)
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return raddr_a;
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else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM)
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return 32 + raddr_b;
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else if (add_a <= QPU_MUX_R3)
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return 64 + add_a;
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else
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return ~0;
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}
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static bool
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is_tmu_submit(uint32_t waddr)
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{
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return (waddr == QPU_W_TMU0_S ||
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waddr == QPU_W_TMU1_S);
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}
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static bool
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is_tmu_write(uint32_t waddr)
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{
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return (waddr >= QPU_W_TMU0_S &&
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waddr <= QPU_W_TMU1_B);
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}
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static bool
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record_texture_sample(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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int tmu)
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{
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uint32_t s = validated_shader->num_texture_samples;
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int i;
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struct vc4_texture_sample_info *temp_samples;
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temp_samples = krealloc(validated_shader->texture_samples,
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(s + 1) * sizeof(*temp_samples),
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GFP_KERNEL);
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if (!temp_samples)
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return false;
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memcpy(&temp_samples[s],
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&validation_state->tmu_setup[tmu],
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sizeof(*temp_samples));
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validated_shader->num_texture_samples = s + 1;
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validated_shader->texture_samples = temp_samples;
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for (i = 0; i < 4; i++)
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validation_state->tmu_setup[tmu].p_offset[i] = ~0;
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return true;
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}
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static bool
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check_tmu_write(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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bool is_mul)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t waddr = (is_mul ?
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
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QPU_GET_FIELD(inst, QPU_WADDR_ADD));
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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int tmu = waddr > QPU_W_TMU0_B;
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bool submit = is_tmu_submit(waddr);
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bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0;
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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if (is_direct) {
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uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
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uint32_t clamp_reg, clamp_offset;
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if (sig == QPU_SIG_SMALL_IMM) {
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DRM_ERROR("direct TMU read used small immediate\n");
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return false;
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}
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/* Make sure that this texture load is an add of the base
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* address of the UBO to a clamped offset within the UBO.
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*/
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if (is_mul ||
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QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
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DRM_ERROR("direct TMU load wasn't an add\n");
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return false;
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}
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/* We assert that the clamped address is the first
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* argument, and the UBO base address is the second argument.
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* This is arbitrary, but simpler than supporting flipping the
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* two either way.
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*/
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clamp_reg = raddr_add_a_to_live_reg_index(inst);
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if (clamp_reg == ~0) {
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DRM_ERROR("direct TMU load wasn't clamped\n");
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return false;
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}
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clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg];
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if (clamp_offset == ~0) {
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DRM_ERROR("direct TMU load wasn't clamped\n");
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return false;
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}
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/* Store the clamp value's offset in p1 (see reloc_tex() in
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* vc4_validate.c).
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*/
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validation_state->tmu_setup[tmu].p_offset[1] =
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clamp_offset;
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if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
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!(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
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DRM_ERROR("direct TMU load didn't add to a uniform\n");
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return false;
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}
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validation_state->tmu_setup[tmu].is_direct = true;
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} else {
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if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
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raddr_b == QPU_R_UNIF)) {
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DRM_ERROR("uniform read in the same instruction as "
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"texture setup.\n");
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return false;
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}
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}
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if (validation_state->tmu_write_count[tmu] >= 4) {
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DRM_ERROR("TMU%d got too many parameters before dispatch\n",
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tmu);
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return false;
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}
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validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] =
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validated_shader->uniforms_size;
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validation_state->tmu_write_count[tmu]++;
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/* Since direct uses a RADDR uniform reference, it will get counted in
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* check_instruction_reads()
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*/
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if (!is_direct) {
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if (validation_state->needs_uniform_address_update) {
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DRM_ERROR("Texturing with undefined uniform address\n");
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return false;
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}
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validated_shader->uniforms_size += 4;
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}
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if (submit) {
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if (!record_texture_sample(validated_shader,
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validation_state, tmu)) {
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return false;
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}
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validation_state->tmu_write_count[tmu] = 0;
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}
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return true;
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}
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static bool require_uniform_address_uniform(struct vc4_validated_shader_info *validated_shader)
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{
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uint32_t o = validated_shader->num_uniform_addr_offsets;
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uint32_t num_uniforms = validated_shader->uniforms_size / 4;
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validated_shader->uniform_addr_offsets =
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krealloc(validated_shader->uniform_addr_offsets,
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(o + 1) *
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sizeof(*validated_shader->uniform_addr_offsets),
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GFP_KERNEL);
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if (!validated_shader->uniform_addr_offsets)
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return false;
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validated_shader->uniform_addr_offsets[o] = num_uniforms;
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validated_shader->num_uniform_addr_offsets++;
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return true;
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}
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static bool
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validate_uniform_address_write(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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bool is_mul)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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u32 add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
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u32 raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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u32 raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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u32 add_lri = raddr_add_a_to_live_reg_index(inst);
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/* We want our reset to be pointing at whatever uniform follows the
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* uniforms base address.
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*/
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u32 expected_offset = validated_shader->uniforms_size + 4;
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/* We only support absolute uniform address changes, and we
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* require that they be in the current basic block before any
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* of its uniform reads.
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*
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* One could potentially emit more efficient QPU code, by
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* noticing that (say) an if statement does uniform control
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* flow for all threads and that the if reads the same number
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* of uniforms on each side. However, this scheme is easy to
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* validate so it's all we allow for now.
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*/
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if (QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_NONE) {
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DRM_ERROR("uniforms address change must be "
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"normal math\n");
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return false;
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}
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if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
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DRM_ERROR("Uniform address reset must be an ADD.\n");
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return false;
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}
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if (QPU_GET_FIELD(inst, QPU_COND_ADD) != QPU_COND_ALWAYS) {
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DRM_ERROR("Uniform address reset must be unconditional.\n");
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return false;
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}
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if (QPU_GET_FIELD(inst, QPU_PACK) != QPU_PACK_A_NOP &&
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!(inst & QPU_PM)) {
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DRM_ERROR("No packing allowed on uniforms reset\n");
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return false;
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}
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if (add_lri == -1) {
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DRM_ERROR("First argument of uniform address write must be "
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"an immediate value.\n");
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return false;
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}
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if (validation_state->live_immediates[add_lri] != expected_offset) {
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DRM_ERROR("Resetting uniforms with offset %db instead of %db\n",
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validation_state->live_immediates[add_lri],
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expected_offset);
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return false;
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}
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if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
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!(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
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DRM_ERROR("Second argument of uniform address write must be "
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"a uniform.\n");
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return false;
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}
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validation_state->needs_uniform_address_update = false;
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validation_state->needs_uniform_address_for_loop = false;
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return require_uniform_address_uniform(validated_shader);
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}
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static bool
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check_reg_write(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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bool is_mul)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t waddr = (is_mul ?
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
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QPU_GET_FIELD(inst, QPU_WADDR_ADD));
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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bool ws = inst & QPU_WS;
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bool is_b = is_mul ^ ws;
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u32 lri = waddr_to_live_reg_index(waddr, is_b);
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if (lri != -1) {
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uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
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uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL);
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if (sig == QPU_SIG_LOAD_IMM &&
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QPU_GET_FIELD(inst, QPU_PACK) == QPU_PACK_A_NOP &&
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((is_mul && cond_mul == QPU_COND_ALWAYS) ||
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(!is_mul && cond_add == QPU_COND_ALWAYS))) {
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validation_state->live_immediates[lri] =
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QPU_GET_FIELD(inst, QPU_LOAD_IMM);
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} else {
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validation_state->live_immediates[lri] = ~0;
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}
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}
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switch (waddr) {
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case QPU_W_UNIFORMS_ADDRESS:
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if (is_b) {
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DRM_ERROR("relative uniforms address change "
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"unsupported\n");
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return false;
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}
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return validate_uniform_address_write(validated_shader,
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validation_state,
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is_mul);
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case QPU_W_TLB_COLOR_MS:
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case QPU_W_TLB_COLOR_ALL:
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case QPU_W_TLB_Z:
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/* These only interact with the tile buffer, not main memory,
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* so they're safe.
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*/
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return true;
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case QPU_W_TMU0_S:
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case QPU_W_TMU0_T:
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case QPU_W_TMU0_R:
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case QPU_W_TMU0_B:
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case QPU_W_TMU1_S:
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case QPU_W_TMU1_T:
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case QPU_W_TMU1_R:
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case QPU_W_TMU1_B:
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return check_tmu_write(validated_shader, validation_state,
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is_mul);
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case QPU_W_HOST_INT:
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case QPU_W_TMU_NOSWAP:
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case QPU_W_TLB_ALPHA_MASK:
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case QPU_W_MUTEX_RELEASE:
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/* XXX: I haven't thought about these, so don't support them
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* for now.
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*/
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DRM_ERROR("Unsupported waddr %d\n", waddr);
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return false;
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case QPU_W_VPM_ADDR:
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DRM_ERROR("General VPM DMA unsupported\n");
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return false;
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case QPU_W_VPM:
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case QPU_W_VPMVCD_SETUP:
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/* We allow VPM setup in general, even including VPM DMA
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* configuration setup, because the (unsafe) DMA can only be
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* triggered by QPU_W_VPM_ADDR writes.
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*/
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return true;
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case QPU_W_TLB_STENCIL_SETUP:
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return true;
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}
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return true;
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}
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static void
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track_live_clamps(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
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uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
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uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
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uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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bool ws = inst & QPU_WS;
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uint32_t lri_add_a, lri_add, lri_mul;
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bool add_a_is_min_0;
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/* Check whether OP_ADD's A argumennt comes from a live MAX(x, 0),
|
|
* before we clear previous live state.
|
|
*/
|
|
lri_add_a = raddr_add_a_to_live_reg_index(inst);
|
|
add_a_is_min_0 = (lri_add_a != ~0 &&
|
|
validation_state->live_max_clamp_regs[lri_add_a]);
|
|
|
|
/* Clear live state for registers written by our instruction. */
|
|
lri_add = waddr_to_live_reg_index(waddr_add, ws);
|
|
lri_mul = waddr_to_live_reg_index(waddr_mul, !ws);
|
|
if (lri_mul != ~0) {
|
|
validation_state->live_max_clamp_regs[lri_mul] = false;
|
|
validation_state->live_min_clamp_offsets[lri_mul] = ~0;
|
|
}
|
|
if (lri_add != ~0) {
|
|
validation_state->live_max_clamp_regs[lri_add] = false;
|
|
validation_state->live_min_clamp_offsets[lri_add] = ~0;
|
|
} else {
|
|
/* Nothing further to do for live tracking, since only ADDs
|
|
* generate new live clamp registers.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
/* Now, handle remaining live clamp tracking for the ADD operation. */
|
|
|
|
if (cond_add != QPU_COND_ALWAYS)
|
|
return;
|
|
|
|
if (op_add == QPU_A_MAX) {
|
|
/* Track live clamps of a value to a minimum of 0 (in either
|
|
* arg).
|
|
*/
|
|
if (sig != QPU_SIG_SMALL_IMM || raddr_b != 0 ||
|
|
(add_a != QPU_MUX_B && add_b != QPU_MUX_B)) {
|
|
return;
|
|
}
|
|
|
|
validation_state->live_max_clamp_regs[lri_add] = true;
|
|
} else if (op_add == QPU_A_MIN) {
|
|
/* Track live clamps of a value clamped to a minimum of 0 and
|
|
* a maximum of some uniform's offset.
|
|
*/
|
|
if (!add_a_is_min_0)
|
|
return;
|
|
|
|
if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
|
|
!(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
|
|
sig != QPU_SIG_SMALL_IMM)) {
|
|
return;
|
|
}
|
|
|
|
validation_state->live_min_clamp_offsets[lri_add] =
|
|
validated_shader->uniforms_size;
|
|
}
|
|
}
|
|
|
|
static bool
|
|
check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
|
|
struct vc4_shader_validation_state *validation_state)
|
|
{
|
|
uint64_t inst = validation_state->shader[validation_state->ip];
|
|
uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
|
|
uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
|
|
bool ok;
|
|
|
|
if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
|
|
DRM_ERROR("ADD and MUL both set up textures\n");
|
|
return false;
|
|
}
|
|
|
|
ok = (check_reg_write(validated_shader, validation_state, false) &&
|
|
check_reg_write(validated_shader, validation_state, true));
|
|
|
|
track_live_clamps(validated_shader, validation_state);
|
|
|
|
return ok;
|
|
}
|
|
|
|
static bool
|
|
check_branch(uint64_t inst,
|
|
struct vc4_validated_shader_info *validated_shader,
|
|
struct vc4_shader_validation_state *validation_state,
|
|
int ip)
|
|
{
|
|
int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET);
|
|
uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
|
|
uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
|
|
|
|
if ((int)branch_imm < 0)
|
|
validation_state->needs_uniform_address_for_loop = true;
|
|
|
|
/* We don't want to have to worry about validation of this, and
|
|
* there's no need for it.
|
|
*/
|
|
if (waddr_add != QPU_W_NOP || waddr_mul != QPU_W_NOP) {
|
|
DRM_ERROR("branch instruction at %d wrote a register.\n",
|
|
validation_state->ip);
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
check_instruction_reads(struct vc4_validated_shader_info *validated_shader,
|
|
struct vc4_shader_validation_state *validation_state)
|
|
{
|
|
uint64_t inst = validation_state->shader[validation_state->ip];
|
|
uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
|
|
uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
|
|
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
|
|
|
|
if (raddr_a == QPU_R_UNIF ||
|
|
(raddr_b == QPU_R_UNIF && sig != QPU_SIG_SMALL_IMM)) {
|
|
/* This can't overflow the uint32_t, because we're reading 8
|
|
* bytes of instruction to increment by 4 here, so we'd
|
|
* already be OOM.
|
|
*/
|
|
validated_shader->uniforms_size += 4;
|
|
|
|
if (validation_state->needs_uniform_address_update) {
|
|
DRM_ERROR("Uniform read with undefined uniform "
|
|
"address\n");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/* Make sure that all branches are absolute and point within the shader, and
|
|
* note their targets for later.
|
|
*/
|
|
static bool
|
|
vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
|
|
{
|
|
uint32_t max_branch_target = 0;
|
|
bool found_shader_end = false;
|
|
int ip;
|
|
int shader_end_ip = 0;
|
|
int last_branch = -2;
|
|
|
|
for (ip = 0; ip < validation_state->max_ip; ip++) {
|
|
uint64_t inst = validation_state->shader[ip];
|
|
int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET);
|
|
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
|
|
uint32_t after_delay_ip = ip + 4;
|
|
uint32_t branch_target_ip;
|
|
|
|
if (sig == QPU_SIG_PROG_END) {
|
|
shader_end_ip = ip;
|
|
found_shader_end = true;
|
|
continue;
|
|
}
|
|
|
|
if (sig != QPU_SIG_BRANCH)
|
|
continue;
|
|
|
|
if (ip - last_branch < 4) {
|
|
DRM_ERROR("Branch at %d during delay slots\n", ip);
|
|
return false;
|
|
}
|
|
last_branch = ip;
|
|
|
|
if (inst & QPU_BRANCH_REG) {
|
|
DRM_ERROR("branching from register relative "
|
|
"not supported\n");
|
|
return false;
|
|
}
|
|
|
|
if (!(inst & QPU_BRANCH_REL)) {
|
|
DRM_ERROR("relative branching required\n");
|
|
return false;
|
|
}
|
|
|
|
/* The actual branch target is the instruction after the delay
|
|
* slots, plus whatever byte offset is in the low 32 bits of
|
|
* the instruction. Make sure we're not branching beyond the
|
|
* end of the shader object.
|
|
*/
|
|
if (branch_imm % sizeof(inst) != 0) {
|
|
DRM_ERROR("branch target not aligned\n");
|
|
return false;
|
|
}
|
|
|
|
branch_target_ip = after_delay_ip + (branch_imm >> 3);
|
|
if (branch_target_ip >= validation_state->max_ip) {
|
|
DRM_ERROR("Branch at %d outside of shader (ip %d/%d)\n",
|
|
ip, branch_target_ip,
|
|
validation_state->max_ip);
|
|
return false;
|
|
}
|
|
set_bit(branch_target_ip, validation_state->branch_targets);
|
|
|
|
/* Make sure that the non-branching path is also not outside
|
|
* the shader.
|
|
*/
|
|
if (after_delay_ip >= validation_state->max_ip) {
|
|
DRM_ERROR("Branch at %d continues past shader end "
|
|
"(%d/%d)\n",
|
|
ip, after_delay_ip, validation_state->max_ip);
|
|
return false;
|
|
}
|
|
set_bit(after_delay_ip, validation_state->branch_targets);
|
|
max_branch_target = max(max_branch_target, after_delay_ip);
|
|
|
|
/* There are two delay slots after program end is signaled
|
|
* that are still executed, then we're finished.
|
|
*/
|
|
if (found_shader_end && ip == shader_end_ip + 2)
|
|
break;
|
|
}
|
|
|
|
if (max_branch_target > shader_end_ip) {
|
|
DRM_ERROR("Branch landed after QPU_SIG_PROG_END");
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/* Resets any known state for the shader, used when we may be branched to from
|
|
* multiple locations in the program (or at shader start).
|
|
*/
|
|
static void
|
|
reset_validation_state(struct vc4_shader_validation_state *validation_state)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 8; i++)
|
|
validation_state->tmu_setup[i / 4].p_offset[i % 4] = ~0;
|
|
|
|
for (i = 0; i < LIVE_REG_COUNT; i++) {
|
|
validation_state->live_min_clamp_offsets[i] = ~0;
|
|
validation_state->live_max_clamp_regs[i] = false;
|
|
validation_state->live_immediates[i] = ~0;
|
|
}
|
|
}
|
|
|
|
static bool
|
|
texturing_in_progress(struct vc4_shader_validation_state *validation_state)
|
|
{
|
|
return (validation_state->tmu_write_count[0] != 0 ||
|
|
validation_state->tmu_write_count[1] != 0);
|
|
}
|
|
|
|
static bool
|
|
vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state)
|
|
{
|
|
uint32_t ip = validation_state->ip;
|
|
|
|
if (!test_bit(ip, validation_state->branch_targets))
|
|
return true;
|
|
|
|
if (texturing_in_progress(validation_state)) {
|
|
DRM_ERROR("Branch target landed during TMU setup\n");
|
|
return false;
|
|
}
|
|
|
|
/* Reset our live values tracking, since this instruction may have
|
|
* multiple predecessors.
|
|
*
|
|
* One could potentially do analysis to determine that, for
|
|
* example, all predecessors have a live max clamp in the same
|
|
* register, but we don't bother with that.
|
|
*/
|
|
reset_validation_state(validation_state);
|
|
|
|
/* Since we've entered a basic block from potentially multiple
|
|
* predecessors, we need the uniforms address to be updated before any
|
|
* unforms are read. We require that after any branch point, the next
|
|
* uniform to be loaded is a uniform address offset. That uniform's
|
|
* offset will be marked by the uniform address register write
|
|
* validation, or a one-off the end-of-program check.
|
|
*/
|
|
validation_state->needs_uniform_address_update = true;
|
|
|
|
return true;
|
|
}
|
|
|
|
struct vc4_validated_shader_info *
|
|
vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
|
|
{
|
|
bool found_shader_end = false;
|
|
int shader_end_ip = 0;
|
|
uint32_t ip;
|
|
struct vc4_validated_shader_info *validated_shader = NULL;
|
|
struct vc4_shader_validation_state validation_state;
|
|
|
|
memset(&validation_state, 0, sizeof(validation_state));
|
|
validation_state.shader = shader_obj->vaddr;
|
|
validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
|
|
|
|
reset_validation_state(&validation_state);
|
|
|
|
validation_state.branch_targets =
|
|
kcalloc(BITS_TO_LONGS(validation_state.max_ip),
|
|
sizeof(unsigned long), GFP_KERNEL);
|
|
if (!validation_state.branch_targets)
|
|
goto fail;
|
|
|
|
validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
|
|
if (!validated_shader)
|
|
goto fail;
|
|
|
|
if (!vc4_validate_branches(&validation_state))
|
|
goto fail;
|
|
|
|
for (ip = 0; ip < validation_state.max_ip; ip++) {
|
|
uint64_t inst = validation_state.shader[ip];
|
|
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
|
|
|
|
validation_state.ip = ip;
|
|
|
|
if (!vc4_handle_branch_target(&validation_state))
|
|
goto fail;
|
|
|
|
switch (sig) {
|
|
case QPU_SIG_NONE:
|
|
case QPU_SIG_WAIT_FOR_SCOREBOARD:
|
|
case QPU_SIG_SCOREBOARD_UNLOCK:
|
|
case QPU_SIG_COLOR_LOAD:
|
|
case QPU_SIG_LOAD_TMU0:
|
|
case QPU_SIG_LOAD_TMU1:
|
|
case QPU_SIG_PROG_END:
|
|
case QPU_SIG_SMALL_IMM:
|
|
if (!check_instruction_writes(validated_shader,
|
|
&validation_state)) {
|
|
DRM_ERROR("Bad write at ip %d\n", ip);
|
|
goto fail;
|
|
}
|
|
|
|
if (!check_instruction_reads(validated_shader,
|
|
&validation_state))
|
|
goto fail;
|
|
|
|
if (sig == QPU_SIG_PROG_END) {
|
|
found_shader_end = true;
|
|
shader_end_ip = ip;
|
|
}
|
|
|
|
break;
|
|
|
|
case QPU_SIG_LOAD_IMM:
|
|
if (!check_instruction_writes(validated_shader,
|
|
&validation_state)) {
|
|
DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
|
|
goto fail;
|
|
}
|
|
break;
|
|
|
|
case QPU_SIG_BRANCH:
|
|
if (!check_branch(inst, validated_shader,
|
|
&validation_state, ip))
|
|
goto fail;
|
|
break;
|
|
default:
|
|
DRM_ERROR("Unsupported QPU signal %d at "
|
|
"instruction %d\n", sig, ip);
|
|
goto fail;
|
|
}
|
|
|
|
/* There are two delay slots after program end is signaled
|
|
* that are still executed, then we're finished.
|
|
*/
|
|
if (found_shader_end && ip == shader_end_ip + 2)
|
|
break;
|
|
}
|
|
|
|
if (ip == validation_state.max_ip) {
|
|
DRM_ERROR("shader failed to terminate before "
|
|
"shader BO end at %zd\n",
|
|
shader_obj->base.size);
|
|
goto fail;
|
|
}
|
|
|
|
/* If we did a backwards branch and we haven't emitted a uniforms
|
|
* reset since then, we still need the uniforms stream to have the
|
|
* uniforms address available so that the backwards branch can do its
|
|
* uniforms reset.
|
|
*
|
|
* We could potentially prove that the backwards branch doesn't
|
|
* contain any uses of uniforms until program exit, but that doesn't
|
|
* seem to be worth the trouble.
|
|
*/
|
|
if (validation_state.needs_uniform_address_for_loop) {
|
|
if (!require_uniform_address_uniform(validated_shader))
|
|
goto fail;
|
|
validated_shader->uniforms_size += 4;
|
|
}
|
|
|
|
/* Again, no chance of integer overflow here because the worst case
|
|
* scenario is 8 bytes of uniforms plus handles per 8-byte
|
|
* instruction.
|
|
*/
|
|
validated_shader->uniforms_src_size =
|
|
(validated_shader->uniforms_size +
|
|
4 * validated_shader->num_texture_samples);
|
|
|
|
kfree(validation_state.branch_targets);
|
|
|
|
return validated_shader;
|
|
|
|
fail:
|
|
kfree(validation_state.branch_targets);
|
|
if (validated_shader) {
|
|
kfree(validated_shader->texture_samples);
|
|
kfree(validated_shader);
|
|
}
|
|
return NULL;
|
|
}
|