mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 08:26:40 +07:00
91c8a326a1
Since drm_i915_private is now a subclass of drm_device we do not need to
chase the drm_i915_private->dev backpointer and can instead simply
access drm_i915_private->drm directly.
text data bss dec hex filename
1068757
4565 416 1073738 10624a drivers/gpu/drm/i915/i915.ko
1066949 4565 416 1071930 105b3a drivers/gpu/drm/i915/i915.ko
Created by the coccinelle script:
@@
struct drm_i915_private *d;
identifier i;
@@
(
- d->dev->i
+ d->drm.i
|
- d->dev
+ &d->drm
)
and for good measure the dev_priv->dev backpointer was removed entirely.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467711623-2905-4-git-send-email-chris@chris-wilson.co.uk
751 lines
19 KiB
C
751 lines
19 KiB
C
/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2008,2010 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*/
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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struct gmbus_pin {
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const char *name;
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i915_reg_t reg;
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};
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/* Map gmbus pin pairs to names and registers. */
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static const struct gmbus_pin gmbus_pins[] = {
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[GMBUS_PIN_SSC] = { "ssc", GPIOB },
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[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
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[GMBUS_PIN_PANEL] = { "panel", GPIOC },
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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static const struct gmbus_pin gmbus_pins_bdw[] = {
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[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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static const struct gmbus_pin gmbus_pins_skl[] = {
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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static const struct gmbus_pin gmbus_pins_bxt[] = {
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[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
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[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
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};
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/* pin is expected to be valid */
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static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
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if (IS_BROXTON(dev_priv))
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return &gmbus_pins_bxt[pin];
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else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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return &gmbus_pins_skl[pin];
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else if (IS_BROADWELL(dev_priv))
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return &gmbus_pins_bdw[pin];
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else
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return &gmbus_pins[pin];
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}
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bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
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unsigned int size;
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if (IS_BROXTON(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_bxt);
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else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_skl);
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else if (IS_BROADWELL(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_bdw);
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else
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size = ARRAY_SIZE(gmbus_pins);
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return pin < size &&
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i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
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}
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/* Intel GPIO access functions */
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#define I2C_RISEFALL_TIME 10
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static inline struct intel_gmbus *
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to_intel_gmbus(struct i2c_adapter *i2c)
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{
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return container_of(i2c, struct intel_gmbus, adapter);
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}
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void
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intel_i2c_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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I915_WRITE(GMBUS0, 0);
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I915_WRITE(GMBUS4, 0);
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}
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static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
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{
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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if (!IS_PINEVIEW(dev_priv))
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return;
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val = I915_READ(DSPCLK_GATE_D);
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if (enable)
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val |= DPCUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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}
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static u32 get_reserved(struct intel_gmbus *bus)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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struct drm_device *dev = &dev_priv->drm;
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u32 reserved = 0;
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/* On most chips, these bits must be preserved in software. */
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if (!IS_I830(dev) && !IS_845G(dev))
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reserved = I915_READ_NOTRACE(bus->gpio_reg) &
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(GPIO_DATA_PULLUP_DISABLE |
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GPIO_CLOCK_PULLUP_DISABLE);
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return reserved;
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}
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static int get_clock(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
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}
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static int get_data(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
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}
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static void set_clock(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 clock_bits;
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if (state_high)
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clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
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else
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clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
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GPIO_CLOCK_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static void set_data(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 data_bits;
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if (state_high)
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data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
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else
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data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
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GPIO_DATA_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static int
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intel_gpio_pre_xfer(struct i2c_adapter *adapter)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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intel_i2c_reset(&dev_priv->drm);
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intel_i2c_quirk_set(dev_priv, true);
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set_data(bus, 1);
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set_clock(bus, 1);
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udelay(I2C_RISEFALL_TIME);
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return 0;
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}
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static void
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intel_gpio_post_xfer(struct i2c_adapter *adapter)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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set_data(bus, 1);
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set_clock(bus, 1);
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intel_i2c_quirk_set(dev_priv, false);
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}
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static void
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intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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struct i2c_algo_bit_data *algo;
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algo = &bus->bit_algo;
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bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
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i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
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bus->adapter.algo_data = algo;
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algo->setsda = set_data;
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algo->setscl = set_clock;
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algo->getsda = get_data;
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algo->getscl = get_clock;
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algo->pre_xfer = intel_gpio_pre_xfer;
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algo->post_xfer = intel_gpio_post_xfer;
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algo->udelay = I2C_RISEFALL_TIME;
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algo->timeout = usecs_to_jiffies(2200);
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algo->data = bus;
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}
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static int
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gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
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u32 gmbus2_status,
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u32 gmbus4_irq_en)
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{
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int i;
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u32 gmbus2 = 0;
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DEFINE_WAIT(wait);
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if (!HAS_GMBUS_IRQ(dev_priv))
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gmbus4_irq_en = 0;
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/* Important: The hw handles only the first bit, so set only one! Since
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* we also need to check for NAKs besides the hw ready/idle signal, we
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* need to wake up periodically and check that ourselves. */
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I915_WRITE(GMBUS4, gmbus4_irq_en);
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for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
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prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
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TASK_UNINTERRUPTIBLE);
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gmbus2 = I915_READ_NOTRACE(GMBUS2);
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if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
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break;
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schedule_timeout(1);
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}
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finish_wait(&dev_priv->gmbus_wait_queue, &wait);
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I915_WRITE(GMBUS4, 0);
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if (gmbus2 & GMBUS_SATOER)
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return -ENXIO;
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if (gmbus2 & gmbus2_status)
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return 0;
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return -ETIMEDOUT;
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}
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static int
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gmbus_wait_idle(struct drm_i915_private *dev_priv)
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{
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int ret;
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if (!HAS_GMBUS_IRQ(dev_priv))
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return intel_wait_for_register(dev_priv,
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GMBUS2, GMBUS_ACTIVE, 0,
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10);
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/* Important: The hw handles only the first bit, so set only one! */
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I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
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ret = wait_event_timeout(dev_priv->gmbus_wait_queue,
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(I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0,
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msecs_to_jiffies_timeout(10));
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I915_WRITE(GMBUS4, 0);
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if (ret)
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return 0;
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else
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return -ETIMEDOUT;
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}
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static int
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gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
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unsigned short addr, u8 *buf, unsigned int len,
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u32 gmbus1_index)
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{
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I915_WRITE(GMBUS1,
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gmbus1_index |
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GMBUS_CYCLE_WAIT |
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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while (len) {
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int ret;
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u32 val, loop = 0;
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ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
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GMBUS_HW_RDY_EN);
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if (ret)
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return ret;
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val = I915_READ(GMBUS3);
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do {
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*buf++ = val & 0xff;
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val >>= 8;
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} while (--len && ++loop < 4);
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}
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return 0;
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}
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static int
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gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
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u32 gmbus1_index)
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{
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u8 *buf = msg->buf;
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unsigned int rx_size = msg->len;
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unsigned int len;
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int ret;
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do {
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len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
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ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
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buf, len, gmbus1_index);
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if (ret)
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return ret;
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rx_size -= len;
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buf += len;
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} while (rx_size != 0);
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return 0;
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}
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static int
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gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
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unsigned short addr, u8 *buf, unsigned int len)
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{
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unsigned int chunk_size = len;
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u32 val, loop;
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val = loop = 0;
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while (len && loop < 4) {
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val |= *buf++ << (8 * loop++);
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len -= 1;
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}
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I915_WRITE(GMBUS3, val);
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I915_WRITE(GMBUS1,
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GMBUS_CYCLE_WAIT |
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(chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
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(addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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while (len) {
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int ret;
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val = loop = 0;
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do {
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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I915_WRITE(GMBUS3, val);
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ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
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GMBUS_HW_RDY_EN);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int
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gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
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{
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u8 *buf = msg->buf;
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unsigned int tx_size = msg->len;
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unsigned int len;
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int ret;
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do {
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len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
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ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
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if (ret)
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return ret;
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buf += len;
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tx_size -= len;
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} while (tx_size != 0);
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return 0;
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}
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/*
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* The gmbus controller can combine a 1 or 2 byte write with a read that
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* immediately follows it by using an "INDEX" cycle.
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*/
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static bool
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gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
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{
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return (i + 1 < num &&
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!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
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(msgs[i + 1].flags & I2C_M_RD));
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}
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static int
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gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
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{
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u32 gmbus1_index = 0;
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u32 gmbus5 = 0;
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int ret;
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if (msgs[0].len == 2)
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gmbus5 = GMBUS_2BYTE_INDEX_EN |
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msgs[0].buf[1] | (msgs[0].buf[0] << 8);
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if (msgs[0].len == 1)
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gmbus1_index = GMBUS_CYCLE_INDEX |
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(msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
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/* GMBUS5 holds 16-bit index */
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if (gmbus5)
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I915_WRITE(GMBUS5, gmbus5);
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ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
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/* Clear GMBUS5 after each index transfer */
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if (gmbus5)
|
|
I915_WRITE(GMBUS5, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct intel_gmbus *bus = container_of(adapter,
|
|
struct intel_gmbus,
|
|
adapter);
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
int i = 0, inc, try = 0;
|
|
int ret = 0;
|
|
|
|
retry:
|
|
I915_WRITE(GMBUS0, bus->reg0);
|
|
|
|
for (; i < num; i += inc) {
|
|
inc = 1;
|
|
if (gmbus_is_index_read(msgs, i, num)) {
|
|
ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
|
|
inc = 2; /* an index read is two msgs */
|
|
} else if (msgs[i].flags & I2C_M_RD) {
|
|
ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
|
|
} else {
|
|
ret = gmbus_xfer_write(dev_priv, &msgs[i]);
|
|
}
|
|
|
|
if (!ret)
|
|
ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
|
|
GMBUS_HW_WAIT_EN);
|
|
if (ret == -ETIMEDOUT)
|
|
goto timeout;
|
|
else if (ret)
|
|
goto clear_err;
|
|
}
|
|
|
|
/* Generate a STOP condition on the bus. Note that gmbus can't generata
|
|
* a STOP on the very first cycle. To simplify the code we
|
|
* unconditionally generate the STOP condition with an additional gmbus
|
|
* cycle. */
|
|
I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
|
|
|
|
/* Mark the GMBUS interface as disabled after waiting for idle.
|
|
* We will re-enable it at the start of the next xfer,
|
|
* till then let it sleep.
|
|
*/
|
|
if (gmbus_wait_idle(dev_priv)) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
|
|
adapter->name);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
I915_WRITE(GMBUS0, 0);
|
|
ret = ret ?: i;
|
|
goto out;
|
|
|
|
clear_err:
|
|
/*
|
|
* Wait for bus to IDLE before clearing NAK.
|
|
* If we clear the NAK while bus is still active, then it will stay
|
|
* active and the next transaction may fail.
|
|
*
|
|
* If no ACK is received during the address phase of a transaction, the
|
|
* adapter must report -ENXIO. It is not clear what to return if no ACK
|
|
* is received at other times. But we have to be careful to not return
|
|
* spurious -ENXIO because that will prevent i2c and drm edid functions
|
|
* from retrying. So return -ENXIO only when gmbus properly quiescents -
|
|
* timing out seems to happen when there _is_ a ddc chip present, but
|
|
* it's slow responding and only answers on the 2nd retry.
|
|
*/
|
|
ret = -ENXIO;
|
|
if (gmbus_wait_idle(dev_priv)) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
|
|
adapter->name);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
|
|
/* Toggle the Software Clear Interrupt bit. This has the effect
|
|
* of resetting the GMBUS controller and so clearing the
|
|
* BUS_ERROR raised by the slave's NAK.
|
|
*/
|
|
I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
|
|
I915_WRITE(GMBUS1, 0);
|
|
I915_WRITE(GMBUS0, 0);
|
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
|
|
adapter->name, msgs[i].addr,
|
|
(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
|
|
|
|
/*
|
|
* Passive adapters sometimes NAK the first probe. Retry the first
|
|
* message once on -ENXIO for GMBUS transfers; the bit banging algorithm
|
|
* has retries internally. See also the retry loop in
|
|
* drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
|
|
*/
|
|
if (ret == -ENXIO && i == 0 && try++ == 0) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
|
|
adapter->name);
|
|
goto retry;
|
|
}
|
|
|
|
goto out;
|
|
|
|
timeout:
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
|
|
bus->adapter.name, bus->reg0 & 0xff);
|
|
I915_WRITE(GMBUS0, 0);
|
|
|
|
/*
|
|
* Hardware may not support GMBUS over these pins? Try GPIO bitbanging
|
|
* instead. Use EAGAIN to have i2c core retry.
|
|
*/
|
|
ret = -EAGAIN;
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
|
|
adapter);
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
int ret;
|
|
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
|
|
mutex_lock(&dev_priv->gmbus_mutex);
|
|
|
|
if (bus->force_bit) {
|
|
ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
|
|
if (ret < 0)
|
|
bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
|
|
} else {
|
|
ret = do_gmbus_xfer(adapter, msgs, num);
|
|
if (ret == -EAGAIN)
|
|
bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
|
|
}
|
|
|
|
mutex_unlock(&dev_priv->gmbus_mutex);
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static u32 gmbus_func(struct i2c_adapter *adapter)
|
|
{
|
|
return i2c_bit_algo.functionality(adapter) &
|
|
(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
|
|
/* I2C_FUNC_10BIT_ADDR | */
|
|
I2C_FUNC_SMBUS_READ_BLOCK_DATA |
|
|
I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
|
|
}
|
|
|
|
static const struct i2c_algorithm gmbus_algorithm = {
|
|
.master_xfer = gmbus_xfer,
|
|
.functionality = gmbus_func
|
|
};
|
|
|
|
/**
|
|
* intel_gmbus_setup - instantiate all Intel i2c GMBuses
|
|
* @dev: DRM device
|
|
*/
|
|
int intel_setup_gmbus(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct intel_gmbus *bus;
|
|
unsigned int pin;
|
|
int ret;
|
|
|
|
if (HAS_PCH_NOP(dev))
|
|
return 0;
|
|
|
|
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
|
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
|
|
else if (!HAS_GMCH_DISPLAY(dev_priv))
|
|
dev_priv->gpio_mmio_base =
|
|
i915_mmio_reg_offset(PCH_GPIOA) -
|
|
i915_mmio_reg_offset(GPIOA);
|
|
|
|
mutex_init(&dev_priv->gmbus_mutex);
|
|
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
|
|
|
|
for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
|
|
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
|
|
continue;
|
|
|
|
bus = &dev_priv->gmbus[pin];
|
|
|
|
bus->adapter.owner = THIS_MODULE;
|
|
bus->adapter.class = I2C_CLASS_DDC;
|
|
snprintf(bus->adapter.name,
|
|
sizeof(bus->adapter.name),
|
|
"i915 gmbus %s",
|
|
get_gmbus_pin(dev_priv, pin)->name);
|
|
|
|
bus->adapter.dev.parent = &dev->pdev->dev;
|
|
bus->dev_priv = dev_priv;
|
|
|
|
bus->adapter.algo = &gmbus_algorithm;
|
|
|
|
/*
|
|
* We wish to retry with bit banging
|
|
* after a timed out GMBUS attempt.
|
|
*/
|
|
bus->adapter.retries = 1;
|
|
|
|
/* By default use a conservative clock rate */
|
|
bus->reg0 = pin | GMBUS_RATE_100KHZ;
|
|
|
|
/* gmbus seems to be broken on i830 */
|
|
if (IS_I830(dev))
|
|
bus->force_bit = 1;
|
|
|
|
intel_gpio_setup(bus, pin);
|
|
|
|
ret = i2c_add_adapter(&bus->adapter);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
intel_i2c_reset(&dev_priv->drm);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
while (pin--) {
|
|
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
|
|
continue;
|
|
|
|
bus = &dev_priv->gmbus[pin];
|
|
i2c_del_adapter(&bus->adapter);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
|
|
unsigned int pin)
|
|
{
|
|
if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
|
|
return NULL;
|
|
|
|
return &dev_priv->gmbus[pin].adapter;
|
|
}
|
|
|
|
void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
|
|
{
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
|
|
}
|
|
|
|
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
|
|
{
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
mutex_lock(&dev_priv->gmbus_mutex);
|
|
|
|
bus->force_bit += force_bit ? 1 : -1;
|
|
DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
|
|
force_bit ? "en" : "dis", adapter->name,
|
|
bus->force_bit);
|
|
|
|
mutex_unlock(&dev_priv->gmbus_mutex);
|
|
}
|
|
|
|
void intel_teardown_gmbus(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct intel_gmbus *bus;
|
|
unsigned int pin;
|
|
|
|
for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
|
|
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
|
|
continue;
|
|
|
|
bus = &dev_priv->gmbus[pin];
|
|
i2c_del_adapter(&bus->adapter);
|
|
}
|
|
}
|