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8bd26e3a7e
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0
("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code. It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
242 lines
5.7 KiB
C
242 lines
5.7 KiB
C
/* linux/arch/arm/mach-exynos4/platsmp.c
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/firmware.h>
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#include <mach/hardware.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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#include <plat/cpu.h>
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#include "common.h"
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extern void exynos4_secondary_startup(void);
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static inline void __iomem *cpu_boot_reg_base(void)
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{
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
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return S5P_INFORM5;
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return S5P_VA_SYSRAM;
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}
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static inline void __iomem *cpu_boot_reg(int cpu)
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{
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void __iomem *boot_reg;
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boot_reg = cpu_boot_reg_base();
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if (soc_is_exynos4412())
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boot_reg += 4*cpu;
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else if (soc_is_exynos5420())
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boot_reg += 4;
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return boot_reg;
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}
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)(S5P_VA_SCU);
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}
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static DEFINE_SPINLOCK(boot_lock);
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static void exynos_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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unsigned long phys_cpu = cpu_logical_map(cpu);
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(phys_cpu);
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if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
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__raw_writel(S5P_CORE_LOCAL_PWR_EN,
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S5P_ARM_CORE1_CONFIGURATION);
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timeout = 10;
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/* wait max 10 ms until cpu1 is on */
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while ((__raw_readl(S5P_ARM_CORE1_STATUS)
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& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
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if (timeout-- == 0)
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break;
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mdelay(1);
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}
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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unsigned long boot_addr;
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smp_rmb();
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boot_addr = virt_to_phys(exynos4_secondary_startup);
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/*
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* Try to set boot address using firmware first
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* and fall back to boot register if it fails.
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*/
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if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
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__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
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call_firmware_op(cpu_boot, phys_cpu);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init exynos_smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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else
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/*
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* CPU Nodes are passed thru DT and set_cpu_possible
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* is set by "arm_dt_init_cpu_maps".
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*/
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return;
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/* sanity check */
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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{
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int i;
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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scu_enable(scu_base_addr());
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/*
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* Write the address of secondary startup into the
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* system-wide flags register. The boot monitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*
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* Try using firmware operation first and fall back to
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* boot register if it fails.
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*/
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for (i = 1; i < max_cpus; ++i) {
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unsigned long phys_cpu;
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unsigned long boot_addr;
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phys_cpu = cpu_logical_map(i);
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boot_addr = virt_to_phys(exynos4_secondary_startup);
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if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
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__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
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}
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}
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struct smp_operations exynos_smp_ops __initdata = {
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.smp_init_cpus = exynos_smp_init_cpus,
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.smp_prepare_cpus = exynos_smp_prepare_cpus,
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.smp_secondary_init = exynos_secondary_init,
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.smp_boot_secondary = exynos_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = exynos_cpu_die,
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#endif
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};
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