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049331f277
The FSGSBASE series turned out to have serious bugs and there is still an open issue which is not fully understood yet. The confidence in those changes has become close to zero especially as the test cases which have been shipped with that series were obviously never run before sending the final series out to LKML. ./fsgsbase_64 >/dev/null Segmentation fault As the merge window is close, the only sane decision is to revert FSGSBASE support. The revert is necessary as this branch has been merged into perf/core already and rebasing all of that a few days before the merge window is not the most brilliant idea. I could definitely slap myself for not noticing the test case fail when merging that series, but TBH my expectations weren't that low back then. Won't happen again. Revert the following commits:539bca535d("x86/entry/64: Fix and clean up paranoid_exit")2c7b5ac5d5("Documentation/x86/64: Add documentation for GS/FS addressing mode")f987c955c7("x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2")2032f1f96e("x86/cpu: Enable FSGSBASE on 64bit by default and add a chicken bit")5bf0cab60e("x86/entry/64: Document GSBASE handling in the paranoid path")708078f657("x86/entry/64: Handle FSGSBASE enabled paranoid entry/exit")79e1932fa3("x86/entry/64: Introduce the FIND_PERCPU_BASE macro")1d07316b13("x86/entry/64: Switch CR3 before SWAPGS in paranoid entry")f60a83df45("x86/process/64: Use FSGSBASE instructions on thread copy and ptrace")1ab5f3f7fe("x86/process/64: Use FSBSBASE in switch_to() if available")a86b462513("x86/fsgsbase/64: Enable FSGSBASE instructions in helper functions")8b71340d70("x86/fsgsbase/64: Add intrinsics for FSGSBASE instructions")b64ed19b93("x86/cpu: Add 'unsafe_fsgsbase' to enable CR4.FSGSBASE") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Ingo Molnar <mingo@kernel.org> Cc: Chang S. Bae <chang.seok.bae@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ravi Shankar <ravi.v.shankar@intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_FSGSBASE_H
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#define _ASM_FSGSBASE_H
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_X86_64
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#include <asm/msr-index.h>
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/*
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* Read/write a task's FSBASE or GSBASE. This returns the value that
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* the FS/GS base would have (if the task were to be resumed). These
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* work on the current task or on a non-running (typically stopped
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* ptrace child) task.
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*/
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extern unsigned long x86_fsbase_read_task(struct task_struct *task);
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extern unsigned long x86_gsbase_read_task(struct task_struct *task);
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extern void x86_fsbase_write_task(struct task_struct *task, unsigned long fsbase);
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extern void x86_gsbase_write_task(struct task_struct *task, unsigned long gsbase);
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/* Helper functions for reading/writing FS/GS base */
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static inline unsigned long x86_fsbase_read_cpu(void)
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{
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unsigned long fsbase;
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rdmsrl(MSR_FS_BASE, fsbase);
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return fsbase;
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}
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static inline unsigned long x86_gsbase_read_cpu_inactive(void)
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{
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unsigned long gsbase;
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rdmsrl(MSR_KERNEL_GS_BASE, gsbase);
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return gsbase;
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}
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static inline void x86_fsbase_write_cpu(unsigned long fsbase)
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{
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wrmsrl(MSR_FS_BASE, fsbase);
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}
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static inline void x86_gsbase_write_cpu_inactive(unsigned long gsbase)
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{
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wrmsrl(MSR_KERNEL_GS_BASE, gsbase);
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}
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#endif /* CONFIG_X86_64 */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_FSGSBASE_H */
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