mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 01:56:42 +07:00
6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
388 lines
10 KiB
ArmAsm
388 lines
10 KiB
ArmAsm
/*
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* OMAP44xx sleep code.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/smp_scu.h>
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#include <asm/memory.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "omap-secure.h"
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#include "common.h"
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#include "omap44xx.h"
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#include "omap4-sar-layout.h"
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#if defined(CONFIG_SMP) && defined(CONFIG_PM)
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.macro DO_SMC
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dsb
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smc #0
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dsb
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.endm
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ppa_zero_params:
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.word 0x0
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ppa_por_params:
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.word 1, 0
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#ifdef CONFIG_ARCH_OMAP4
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/*
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* =============================
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* == CPU suspend finisher ==
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* =============================
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*
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* void omap4_finish_suspend(unsigned long cpu_state)
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*
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* This function code saves the CPU context and performs the CPU
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* power down sequence. Calling WFI effectively changes the CPU
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* power domains states to the desired target power state.
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*
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* @cpu_state : contains context save state (r0)
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* 0 - No context lost
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* 1 - CPUx L1 and logic lost: MPUSS CSWR
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* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
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* 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
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* @return: This function never returns for CPU OFF and DORMANT power states.
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* Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
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* from this follows a full CPU reset path via ROM code to CPU restore code.
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* The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
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* It returns to the caller for CPU INACTIVE and ON power states or in case
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* CPU failed to transition to targeted OFF/DORMANT state.
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*
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* omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
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* stack frame and it expects the caller to take care of it. Hence the entire
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* stack frame is saved to avoid possible stack corruption.
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*/
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ENTRY(omap4_finish_suspend)
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stmfd sp!, {r4-r12, lr}
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cmp r0, #0x0
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beq do_WFI @ No lowpower state, jump to WFI
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/*
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* Flush all data from the L1 data cache before disabling
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* SCTLR.C bit.
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*/
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bl omap4_get_sar_ram_base
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ldr r9, [r0, #OMAP_TYPE_OFFSET]
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cmp r9, #0x1 @ Check for HS device
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bne skip_secure_l1_clean
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mov r0, #SCU_PM_NORMAL
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mov r1, #0xFF @ clean seucre L1
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stmfd r13!, {r4-r12, r14}
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ldr r12, =OMAP4_MON_SCU_PWR_INDEX
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DO_SMC
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ldmfd r13!, {r4-r12, r14}
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skip_secure_l1_clean:
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bl v7_flush_dcache_all
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/*
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* Clear the SCTLR.C bit to prevent further data cache
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* allocation. Clearing SCTLR.C would make all the data accesses
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* strongly ordered and would not hit the cache.
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 2) @ Disable the C bit
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mcr p15, 0, r0, c1, c0, 0
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isb
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/*
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* Invalidate L1 data cache. Even though only invalidate is
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* necessary exported flush API is used here. Doing clean
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* on already clean cache would be almost NOP.
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*/
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bl v7_flush_dcache_all
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/*
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* Switch the CPU from Symmetric Multiprocessing (SMP) mode
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* to AsymmetricMultiprocessing (AMP) mode by programming
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* the SCU power status to DORMANT or OFF mode.
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* This enables the CPU to be taken out of coherency by
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* preventing the CPU from receiving cache, TLB, or BTB
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* maintenance operations broadcast by other CPUs in the cluster.
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*/
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bl omap4_get_sar_ram_base
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mov r8, r0
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ldr r9, [r8, #OMAP_TYPE_OFFSET]
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cmp r9, #0x1 @ Check for HS device
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bne scu_gp_set
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mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
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ands r0, r0, #0x0f
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ldreq r0, [r8, #SCU_OFFSET0]
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ldrne r0, [r8, #SCU_OFFSET1]
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mov r1, #0x00
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stmfd r13!, {r4-r12, r14}
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ldr r12, =OMAP4_MON_SCU_PWR_INDEX
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DO_SMC
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ldmfd r13!, {r4-r12, r14}
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b skip_scu_gp_set
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scu_gp_set:
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mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
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ands r0, r0, #0x0f
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ldreq r1, [r8, #SCU_OFFSET0]
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ldrne r1, [r8, #SCU_OFFSET1]
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bl omap4_get_scu_base
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bl scu_power_mode
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skip_scu_gp_set:
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mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
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tst r0, #(1 << 18)
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mrcne p15, 0, r0, c1, c0, 1
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bicne r0, r0, #(1 << 6) @ Disable SMP bit
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mcrne p15, 0, r0, c1, c0, 1
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isb
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dsb
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#ifdef CONFIG_CACHE_L2X0
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/*
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* Clean and invalidate the L2 cache.
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* Common cache-l2x0.c functions can't be used here since it
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* uses spinlocks. We are out of coherency here with data cache
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* disabled. The spinlock implementation uses exclusive load/store
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* instruction which can fail without data cache being enabled.
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* OMAP4 hardware doesn't support exclusive monitor which can
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* overcome exclusive access issue. Because of this, CPU can
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* lead to deadlock.
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*/
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bl omap4_get_sar_ram_base
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mov r8, r0
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mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
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ands r5, r5, #0x0f
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ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
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ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
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cmp r0, #3
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bne do_WFI
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#ifdef CONFIG_PL310_ERRATA_727915
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mov r0, #0x03
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mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
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DO_SMC
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#endif
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bl omap4_get_l2cache_base
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mov r2, r0
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ldr r0, =0xffff
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str r0, [r2, #L2X0_CLEAN_INV_WAY]
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wait:
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ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
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ldr r1, =0xffff
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ands r0, r0, r1
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bne wait
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#ifdef CONFIG_PL310_ERRATA_727915
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mov r0, #0x00
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mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
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DO_SMC
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#endif
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l2x_sync:
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bl omap4_get_l2cache_base
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mov r2, r0
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mov r0, #0x0
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str r0, [r2, #L2X0_CACHE_SYNC]
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sync:
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ldr r0, [r2, #L2X0_CACHE_SYNC]
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ands r0, r0, #0x1
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bne sync
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#endif
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do_WFI:
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bl omap_do_wfi
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/*
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* CPU is here when it failed to enter OFF/DORMANT or
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* no low power state was attempted.
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*/
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mrc p15, 0, r0, c1, c0, 0
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tst r0, #(1 << 2) @ Check C bit enabled?
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orreq r0, r0, #(1 << 2) @ Enable the C bit
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mcreq p15, 0, r0, c1, c0, 0
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isb
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/*
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* Ensure the CPU power state is set to NORMAL in
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* SCU power state so that CPU is back in coherency.
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* In non-coherent mode CPU can lock-up and lead to
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* system deadlock.
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*/
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mrc p15, 0, r0, c1, c0, 1
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tst r0, #(1 << 6) @ Check SMP bit enabled?
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orreq r0, r0, #(1 << 6)
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mcreq p15, 0, r0, c1, c0, 1
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isb
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bl omap4_get_sar_ram_base
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mov r8, r0
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ldr r9, [r8, #OMAP_TYPE_OFFSET]
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cmp r9, #0x1 @ Check for HS device
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bne scu_gp_clear
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mov r0, #SCU_PM_NORMAL
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mov r1, #0x00
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stmfd r13!, {r4-r12, r14}
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ldr r12, =OMAP4_MON_SCU_PWR_INDEX
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DO_SMC
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ldmfd r13!, {r4-r12, r14}
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b skip_scu_gp_clear
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scu_gp_clear:
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bl omap4_get_scu_base
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mov r1, #SCU_PM_NORMAL
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bl scu_power_mode
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skip_scu_gp_clear:
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isb
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dsb
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ldmfd sp!, {r4-r12, pc}
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ENDPROC(omap4_finish_suspend)
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/*
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* ============================
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* == CPU resume entry point ==
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* ============================
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*
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* void omap4_cpu_resume(void)
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*
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* ROM code jumps to this function while waking up from CPU
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* OFF or DORMANT state. Physical address of the function is
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* stored in the SAR RAM while entering to OFF or DORMANT mode.
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* The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
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*/
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ENTRY(omap4_cpu_resume)
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/*
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* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
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* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
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* init and for CPU1, a secure PPA API provided. CPU0 must be ON
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* while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
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* OMAP443X GP devices- SMP bit isn't accessible.
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* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
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*/
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ldr r8, =OMAP44XX_SAR_RAM_BASE
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ldr r9, [r8, #OMAP_TYPE_OFFSET]
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cmp r9, #0x1 @ Skip if GP device
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bne skip_ns_smp_enable
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mrc p15, 0, r0, c0, c0, 5
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ands r0, r0, #0x0f
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beq skip_ns_smp_enable
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ppa_actrl_retry:
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mov r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
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adr r3, ppa_zero_params @ Pointer to parameters
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mov r1, #0x0 @ Process ID
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mov r2, #0x4 @ Flag
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mov r6, #0xff
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mov r12, #0x00 @ Secure Service ID
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DO_SMC
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cmp r0, #0x0 @ API returns 0 on success.
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beq enable_smp_bit
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b ppa_actrl_retry
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enable_smp_bit:
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mrc p15, 0, r0, c1, c0, 1
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tst r0, #(1 << 6) @ Check SMP bit enabled?
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orreq r0, r0, #(1 << 6)
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mcreq p15, 0, r0, c1, c0, 1
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isb
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skip_ns_smp_enable:
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#ifdef CONFIG_CACHE_L2X0
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/*
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* Restore the L2 AUXCTRL and enable the L2 cache.
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* OMAP4_MON_L2X0_AUXCTRL_INDEX = Program the L2X0 AUXCTRL
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* OMAP4_MON_L2X0_CTRL_INDEX = Enable the L2 using L2X0 CTRL
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* register r0 contains value to be programmed.
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* L2 cache is already invalidate by ROM code as part
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* of MPUSS OFF wakeup path.
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*/
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ldr r2, =OMAP44XX_L2CACHE_BASE
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ldr r0, [r2, #L2X0_CTRL]
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and r0, #0x0f
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cmp r0, #1
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beq skip_l2en @ Skip if already enabled
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ldr r3, =OMAP44XX_SAR_RAM_BASE
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ldr r1, [r3, #OMAP_TYPE_OFFSET]
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cmp r1, #0x1 @ Check for HS device
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bne set_gp_por
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ldr r0, =OMAP4_PPA_L2_POR_INDEX
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ldr r1, =OMAP44XX_SAR_RAM_BASE
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ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
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adr r3, ppa_por_params
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str r4, [r3, #0x04]
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mov r1, #0x0 @ Process ID
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mov r2, #0x4 @ Flag
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mov r6, #0xff
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mov r12, #0x00 @ Secure Service ID
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DO_SMC
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b set_aux_ctrl
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set_gp_por:
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ldr r1, =OMAP44XX_SAR_RAM_BASE
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ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
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ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
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DO_SMC
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set_aux_ctrl:
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ldr r1, =OMAP44XX_SAR_RAM_BASE
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ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
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ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
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DO_SMC
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mov r0, #0x1
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ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
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DO_SMC
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skip_l2en:
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#endif
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b cpu_resume @ Jump to generic resume
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ENDPROC(omap4_cpu_resume)
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#endif /* CONFIG_ARCH_OMAP4 */
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#endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
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#ifndef CONFIG_OMAP4_ERRATA_I688
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ENTRY(omap_bus_sync)
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ret lr
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ENDPROC(omap_bus_sync)
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#endif
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ENTRY(omap_do_wfi)
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stmfd sp!, {lr}
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/* Drain interconnect write buffers. */
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bl omap_bus_sync
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/*
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* Execute an ISB instruction to ensure that all of the
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* CP15 register changes have been committed.
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*/
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isb
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/*
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* Execute a barrier instruction to ensure that all cache,
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* TLB and branch predictor maintenance operations issued
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* by any CPU in the cluster have completed.
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*/
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dsb
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dmb
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/*
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* Execute a WFI instruction and wait until the
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* STANDBYWFI output is asserted to indicate that the
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* CPU is in idle and low power state. CPU can specualatively
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* prefetch the instructions so add NOPs after WFI. Sixteen
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* NOPs as per Cortex-A9 pipeline.
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*/
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wfi @ Wait For Interrupt
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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ldmfd sp!, {pc}
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ENDPROC(omap_do_wfi)
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