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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0160a4b689
This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the 'internal-regs' node down into the 'soc' node. This is in preparation to enable the usage of the SPI direct access mode. A follow-up patch will add the static MBus mappings for the SPI devices into the 'reg' property of the SPI controller DT node. By moving these SPI controller nodes, this patch also makes use of the labels rather than keeping the tree structure. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
436 lines
10 KiB
Plaintext
436 lines
10 KiB
Plaintext
/*
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* Device Tree file for Marvell Armada 385 development board
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* (RD-88F6820-GP)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "armada-388.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell Armada 388 DB-88F6820-GP";
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compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x80000000>; /* 2 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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i2c@11000 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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expander0: pca9555@20 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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pinctrl-0 = <&pca0_pins>;
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interrupt-parent = <&gpio0>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x20>;
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};
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expander1: pca9555@21 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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interrupt-parent = <&gpio0>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x21>;
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};
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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};
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};
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serial@12000 {
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/*
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* Exported on the micro USB connector CON16
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* through an FTDI
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*/
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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/* GE1 CON15 */
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ethernet@30000 {
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pinctrl-names = "default";
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pinctrl-0 = <&ge1_rgmii_pins>;
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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bm,pool-short = <3>;
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};
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/* CON4 */
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usb@58000 {
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vcc-supply = <®_usb2_0_vbus>;
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status = "okay";
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};
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/* GE0 CON1 */
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ethernet@70000 {
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pinctrl-names = "default";
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/*
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* The Reference Clock 0 is used to provide a
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* clock to the PHY
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*/
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pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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bm,pool-short = <1>;
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};
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mdio@72004 {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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phy1: ethernet-phy@0 {
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reg = <0>;
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};
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};
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sata@a8000 {
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pinctrl-names = "default";
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pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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sata0: sata-port@0 {
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reg = <0>;
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target-supply = <®_5v_sata0>;
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};
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sata1: sata-port@1 {
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reg = <1>;
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target-supply = <®_5v_sata1>;
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};
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};
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bm@c8000 {
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status = "okay";
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};
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sata@e0000 {
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pinctrl-names = "default";
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pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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sata2: sata-port@0 {
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reg = <0>;
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target-supply = <®_5v_sata2>;
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};
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sata3: sata-port@1 {
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reg = <1>;
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target-supply = <®_5v_sata3>;
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};
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};
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sdhci@d8000 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdhci_pins>;
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no-1-8-v;
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/*
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* A388-GP board v1.5 and higher replace
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* hitherto card detection method based on GPIO
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* with the one using DAT3 pin. As they are
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* incompatible, software-based polling is
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* enabled with 'broken-cd' property. For boards
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* older than v1.5 it can be replaced with:
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* 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
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* whereas for the newer ones following can be
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* used instead:
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* 'dat3-cd;'
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* 'cd-inverted;'
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*/
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broken-cd;
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wp-inverted;
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bus-width = <8>;
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status = "okay";
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};
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/* CON5 */
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usb3@f0000 {
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usb-phy = <&usb2_1_phy>;
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status = "okay";
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};
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/* CON7 */
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usb3@f8000 {
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usb-phy = <&usb3_phy>;
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status = "okay";
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};
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};
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bm-bppi {
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status = "okay";
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};
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pcie-controller {
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status = "okay";
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/*
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* One PCIe units is accessible through
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* standard PCIe slot on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/*
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* The two other PCIe units are accessible
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* through mini PCIe slot on the board.
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*/
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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};
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gpio-fan {
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compatible = "gpio-fan";
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gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
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gpio-fan,speed-map = < 0 0
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3000 1>;
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};
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};
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usb2_1_phy: usb2_1_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <®_usb2_1_vbus>;
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};
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usb3_phy: usb3_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <®_usb3_vbus>;
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};
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reg_usb3_vbus: usb3-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb3-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
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};
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reg_usb2_0_vbus: v5-vbus0 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-vbus0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
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};
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reg_usb2_1_vbus: v5-vbus1 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-vbus1";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
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};
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reg_sata0: pwr-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "pwr_en_sata0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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regulator-boot-on;
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gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
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};
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reg_5v_sata0: v5-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-sata0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_sata0>;
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};
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reg_12v_sata0: v12-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "v12.0-sata0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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vin-supply = <®_sata0>;
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};
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reg_sata1: pwr-sata1 {
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regulator-name = "pwr_en_sata1";
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compatible = "regulator-fixed";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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regulator-boot-on;
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gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
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};
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reg_5v_sata1: v5-sata1 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-sata1";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_sata1>;
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};
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reg_12v_sata1: v12-sata1 {
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compatible = "regulator-fixed";
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regulator-name = "v12.0-sata1";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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vin-supply = <®_sata1>;
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};
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reg_sata2: pwr-sata2 {
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compatible = "regulator-fixed";
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regulator-name = "pwr_en_sata2";
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enable-active-high;
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regulator-boot-on;
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gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
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};
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reg_5v_sata2: v5-sata2 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-sata2";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_sata2>;
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};
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reg_12v_sata2: v12-sata2 {
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compatible = "regulator-fixed";
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regulator-name = "v12.0-sata2";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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vin-supply = <®_sata2>;
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};
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reg_sata3: pwr-sata3 {
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compatible = "regulator-fixed";
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regulator-name = "pwr_en_sata3";
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enable-active-high;
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regulator-boot-on;
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gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
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};
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reg_5v_sata3: v5-sata3 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-sata3";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_sata3>;
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};
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reg_12v_sata3: v12-sata3 {
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compatible = "regulator-fixed";
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regulator-name = "v12.0-sata3";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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vin-supply = <®_sata3>;
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};
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};
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&pinctrl {
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pca0_pins: pca0_pins {
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marvell,pins = "mpp18";
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marvell,function = "gpio";
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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};
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};
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