mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 23:35:26 +07:00
dee02770cd
- Introduce host claiming by context to support blkmq - Preparations for enabling CQE (eMMC CMDQ) requests - Re-factorizations to prepare for blkmq support - Re-factorizations to prepare for CQE support - Fix signal voltage switch for SD cards without power cycle - Convert RPMB to a character device - Export eMMC revision via sysfs - Support eMMC DT binding for fixed driver type - Document mmc_regulator_get_supply() API MMC host: - omap_hsmmc: Updated regulator management for PBIAS - sdhci-omap: Add new OMAP SDHCI driver - meson-mx-sdio: New driver for the Amlogic Meson8 and Meson8b SoCs - sdhci-pci: Add support for Intel CDF - sdhci-acpi: Fix voltage switch for some Intel host controllers - sdhci-msm: Enable delay circuit calibration clocks - sdhci-msm: Manage power IRQ properly - mediatek: Add support of mt2701/mt2712 - mediatek: Updates management of clocks and tunings - mediatek: Upgrade eMMC HS400 support - rtsx_pci: Update tuning for gen3 PCI-Express - renesas_sdhi: Support R-Car Gen[123] fallback compatibility strings - Catch all errors when getting regulators - Various additional improvements and cleanups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaCXiaAAoJEP4mhCVzWIwp+c4P/3UptZJJScU4WFS1zXH8h/YK mYQ4DOCZqQYihKV4ssbAAjmTkT3RdMkl+rq2s5+ZfVbsu57UqeHNaNXBQWirkXCo xBDzZlZFz42g4apKq+ZfmewZTM2fjed8Z7SrDcxPkkyU90QKa/LFFleAyxyXxXr1 ubKHJtev/oWBRxvzvWPYNUI5ExraxGxp2iGvavoYHNcggAgOSBJoKESvF7er5MRK Cx5cuKAESU2dJFQnebjndx3dFgQsZ18RTRXUom50oP3BXF2G3gIBMjxp9VfyuOGV xedyE2ALQxr1bxyWWejMdhhiZ+eNZNtiEJKqJ37ArTeBDyDfO/SDVXlkqkAARlYW rTzh9olfbuhFdCAo2gxAcCaQXnjgQzDDKnQJs++tQVziXGI9ezc44+A6fNh39nre yc/MLIjN96vWRhhFuTeFuENN+n7D2xyy+keXZXrALYYOCPAlKtip6DOgVl3ltNvx K1O7/STqdR4OHLK6vgdzi9ai3PmcmSBQwKCqqCH/7mcFm1xtBcxqdrEwORLQ3lCH c/tl4lJqJR2BD8U9gipjik0ovWb5p2KKAYhjqEY2qMy14OXs2509Y8GcqQRzqcQc FSAfUInooHfDEbUBVsLpTOjMvd6LAx34fTJ9QAanAZ1wdeV8C9DRz3kJh/L/mOmG N7/jyJnMV1Izknmpc2MP =3Gvx -----END PGP SIGNATURE----- Merge tag 'mmc-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC updates from Ulf Hansson: "MMC core: - Introduce host claiming by context to support blkmq - Preparations for enabling CQE (eMMC CMDQ) requests - Re-factorizations to prepare for blkmq support - Re-factorizations to prepare for CQE support - Fix signal voltage switch for SD cards without power cycle - Convert RPMB to a character device - Export eMMC revision via sysfs - Support eMMC DT binding for fixed driver type - Document mmc_regulator_get_supply() API MMC host: - omap_hsmmc: Updated regulator management for PBIAS - sdhci-omap: Add new OMAP SDHCI driver - meson-mx-sdio: New driver for the Amlogic Meson8 and Meson8b SoCs - sdhci-pci: Add support for Intel CDF - sdhci-acpi: Fix voltage switch for some Intel host controllers - sdhci-msm: Enable delay circuit calibration clocks - sdhci-msm: Manage power IRQ properly - mediatek: Add support of mt2701/mt2712 - mediatek: Updates management of clocks and tunings - mediatek: Upgrade eMMC HS400 support - rtsx_pci: Update tuning for gen3 PCI-Express - renesas_sdhi: Support R-Car Gen[123] fallback compatibility strings - Catch all errors when getting regulators - Various additional improvements and cleanups" * tag 'mmc-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (91 commits) sdhci-fujitsu: add support for setting the CMD_DAT_DELAY attribute dt-bindings: sdhci-fujitsu: document cmd-dat-delay property mmc: tmio: Replace msleep() of 20ms or less with usleep_range() mmc: dw_mmc: Convert timers to use timer_setup() mmc: dw_mmc: Cleanup the DTO timer like the CTO one mmc: vub300: Use common code in __download_offload_pseudocode() mmc: tmio: Use common error handling code in tmio_mmc_host_probe() mmc: Convert timers to use timer_setup() mmc: sdhci-acpi: Fix voltage switch for some Intel host controllers mmc: sdhci-acpi: Let devices define their own private data mmc: mediatek: perfer to use rise edge latching for cmd line mmc: mediatek: improve eMMC hs400 mode read performance mmc: mediatek: add latch-ck support mmc: mediatek: add support of source_cg clock mmc: mediatek: add stop_clk fix and enhance_rx support mmc: mediatek: add busy_check support mmc: mediatek: add async fifo and data tune support mmc: mediatek: add pad_tune0 support mmc: mediatek: make hs400_tune_response only for mt8173 arm64: dts: mt8173: remove "mediatek, mt8135-mmc" from mmc nodes ...
181 lines
5.0 KiB
C
181 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SDHCI_PCI_H
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#define __SDHCI_PCI_H
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/*
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* PCI device IDs, sub IDs
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*/
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#define PCI_DEVICE_ID_O2_SDS0 0x8420
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#define PCI_DEVICE_ID_O2_SDS1 0x8421
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#define PCI_DEVICE_ID_O2_FUJIN2 0x8520
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#define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
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#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
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#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
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#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
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#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
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#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
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#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
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#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
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#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
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#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
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#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
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#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
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#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
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#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
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#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
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#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
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#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
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#define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db
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#define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
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#define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
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#define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
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#define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
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#define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
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#define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
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#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
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#define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
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#define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
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#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
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#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
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#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
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#define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4
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#define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5
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#define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
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#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
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#define PCI_DEVICE_ID_VIA_95D0 0x95d0
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#define PCI_DEVICE_ID_REALTEK_5250 0x5250
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#define PCI_SUBDEVICE_ID_NI_7884 0x7884
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/*
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* PCI device class and mask
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*/
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#define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8)
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#define PCI_CLASS_MASK 0xFFFF00
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/*
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* Macros for PCI device-description
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*/
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#define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
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#define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
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#define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
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#define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
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.vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
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.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
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.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
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}
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#define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
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.vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
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.subvendor = _PCI_VEND(subvend), \
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.subdevice = _PCI_SUBDEV(subvend, subdev), \
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.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
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}
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#define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
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.vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
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.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
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.class = (cl), .class_mask = (cl_msk), \
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.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
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}
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/*
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* PCI registers
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*/
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#define PCI_SDHCI_IFPIO 0x00
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#define PCI_SDHCI_IFDMA 0x01
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#define PCI_SDHCI_IFVENDOR 0x02
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#define PCI_SLOT_INFO 0x40 /* 8 bits */
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#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
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#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
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#define MAX_SLOTS 8
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struct sdhci_pci_chip;
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struct sdhci_pci_slot;
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struct sdhci_pci_fixes {
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unsigned int quirks;
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unsigned int quirks2;
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bool allow_runtime_pm;
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bool own_cd_for_runtime_pm;
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int (*probe) (struct sdhci_pci_chip *);
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int (*probe_slot) (struct sdhci_pci_slot *);
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int (*add_host) (struct sdhci_pci_slot *);
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void (*remove_slot) (struct sdhci_pci_slot *, int);
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#ifdef CONFIG_PM_SLEEP
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int (*suspend) (struct sdhci_pci_chip *);
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int (*resume) (struct sdhci_pci_chip *);
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#endif
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#ifdef CONFIG_PM
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int (*runtime_suspend) (struct sdhci_pci_chip *);
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int (*runtime_resume) (struct sdhci_pci_chip *);
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#endif
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const struct sdhci_ops *ops;
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size_t priv_size;
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};
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struct sdhci_pci_slot {
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struct sdhci_pci_chip *chip;
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struct sdhci_host *host;
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struct sdhci_pci_data *data;
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int rst_n_gpio;
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int cd_gpio;
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int cd_irq;
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int cd_idx;
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bool cd_override_level;
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void (*hw_reset)(struct sdhci_host *host);
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unsigned long private[0] ____cacheline_aligned;
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};
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struct sdhci_pci_chip {
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struct pci_dev *pdev;
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unsigned int quirks;
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unsigned int quirks2;
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bool allow_runtime_pm;
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bool pm_retune;
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bool rpm_retune;
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const struct sdhci_pci_fixes *fixes;
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int num_slots; /* Slots on controller */
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struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
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};
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static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
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{
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return (void *)slot->private;
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}
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#ifdef CONFIG_PM_SLEEP
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int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
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#endif
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int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
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int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
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#ifdef CONFIG_PM_SLEEP
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int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
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#endif
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#endif /* __SDHCI_PCI_H */
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