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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8c0236fc46
Clock framework for SPEAr is based upon clkdev framework for ARM Reviewed-by: Linus Walleij <linux.walleij@stericsson.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
436 lines
10 KiB
C
436 lines
10 KiB
C
/*
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* arch/arm/plat-spear/clock.c
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*
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* Clock framework for SPEAr platform
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/bug.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <mach/misc_regs.h>
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#include <plat/clock.h>
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static DEFINE_SPINLOCK(clocks_lock);
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static LIST_HEAD(root_clks);
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static void propagate_rate(struct list_head *);
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static int generic_clk_enable(struct clk *clk)
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{
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unsigned int val;
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if (!clk->en_reg)
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return -EFAULT;
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val = readl(clk->en_reg);
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if (unlikely(clk->flags & RESET_TO_ENABLE))
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val &= ~(1 << clk->en_reg_bit);
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else
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val |= 1 << clk->en_reg_bit;
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writel(val, clk->en_reg);
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return 0;
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}
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static void generic_clk_disable(struct clk *clk)
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{
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unsigned int val;
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if (!clk->en_reg)
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return;
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val = readl(clk->en_reg);
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if (unlikely(clk->flags & RESET_TO_ENABLE))
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val |= 1 << clk->en_reg_bit;
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else
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val &= ~(1 << clk->en_reg_bit);
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writel(val, clk->en_reg);
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}
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/* generic clk ops */
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static struct clkops generic_clkops = {
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.enable = generic_clk_enable,
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.disable = generic_clk_disable,
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};
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/*
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* clk_enable - inform the system when the clock source should be running.
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* @clk: clock source
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*
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* If the clock can not be enabled/disabled, this should return success.
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*
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* Returns success (0) or negative errno.
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*/
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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int ret = 0;
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if (!clk || IS_ERR(clk))
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return -EFAULT;
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->usage_count == 0) {
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if (clk->ops && clk->ops->enable)
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ret = clk->ops->enable(clk);
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}
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clk->usage_count++;
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spin_unlock_irqrestore(&clocks_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_enable);
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/*
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* clk_disable - inform the system when the clock source is no longer required.
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* @clk: clock source
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*
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* Inform the system that a clock source is no longer required by
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* a driver and may be shut down.
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*
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* Implementation detail: if the clock source is shared between
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* multiple drivers, clk_enable() calls must be balanced by the
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* same number of clk_disable() calls for the clock source to be
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* disabled.
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*/
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (!clk || IS_ERR(clk))
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return;
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WARN_ON(clk->usage_count == 0);
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spin_lock_irqsave(&clocks_lock, flags);
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clk->usage_count--;
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if (clk->usage_count == 0) {
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if (clk->ops && clk->ops->disable)
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clk->ops->disable(clk);
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}
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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/**
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* clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
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* This is only valid once the clock source has been enabled.
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* @clk: clock source
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*/
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long flags, rate;
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spin_lock_irqsave(&clocks_lock, flags);
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rate = clk->rate;
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spin_unlock_irqrestore(&clocks_lock, flags);
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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/**
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* clk_set_parent - set the parent clock source for this clock
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* @clk: clock source
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* @parent: parent clock source
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*
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* Returns success (0) or negative errno.
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*/
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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int i, found = 0, val = 0;
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unsigned long flags;
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if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent))
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return -EFAULT;
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if (clk->usage_count)
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return -EBUSY;
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if (!clk->pclk_sel)
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return -EPERM;
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if (clk->pclk == parent)
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return 0;
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for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
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if (clk->pclk_sel->pclk_info[i].pclk == parent) {
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found = 1;
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break;
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}
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}
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if (!found)
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return -EINVAL;
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spin_lock_irqsave(&clocks_lock, flags);
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/* reflect parent change in hardware */
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val = readl(clk->pclk_sel->pclk_sel_reg);
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val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
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val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift;
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writel(val, clk->pclk_sel->pclk_sel_reg);
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spin_unlock_irqrestore(&clocks_lock, flags);
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/* reflect parent change in software */
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clk->recalc(clk);
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propagate_rate(&clk->children);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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/* registers clock in platform clock framework */
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void clk_register(struct clk_lookup *cl)
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{
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struct clk *clk = cl->clk;
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unsigned long flags;
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if (!clk || IS_ERR(clk))
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return;
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spin_lock_irqsave(&clocks_lock, flags);
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INIT_LIST_HEAD(&clk->children);
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if (clk->flags & ALWAYS_ENABLED)
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clk->ops = NULL;
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else if (!clk->ops)
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clk->ops = &generic_clkops;
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/* root clock don't have any parents */
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if (!clk->pclk && !clk->pclk_sel) {
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list_add(&clk->sibling, &root_clks);
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/* add clocks with only one parent to parent's children list */
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} else if (clk->pclk && !clk->pclk_sel) {
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list_add(&clk->sibling, &clk->pclk->children);
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} else {
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/* add clocks with > 1 parent to 1st parent's children list */
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list_add(&clk->sibling,
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&clk->pclk_sel->pclk_info[0].pclk->children);
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}
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spin_unlock_irqrestore(&clocks_lock, flags);
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/* add clock to arm clockdev framework */
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clkdev_add(cl);
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}
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/**
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* propagate_rate - recalculate and propagate all clocks in list head
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*
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* Recalculates all root clocks in list head, which if the clock's .recalc is
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* set correctly, should also propagate their rates.
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*/
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static void propagate_rate(struct list_head *lhead)
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{
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struct clk *clkp, *_temp;
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list_for_each_entry_safe(clkp, _temp, lhead, sibling) {
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if (clkp->recalc)
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clkp->recalc(clkp);
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propagate_rate(&clkp->children);
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}
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}
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/* returns current programmed clocks clock info structure */
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static struct pclk_info *pclk_info_get(struct clk *clk)
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{
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unsigned int mask, i;
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unsigned long flags;
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struct pclk_info *info = NULL;
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spin_lock_irqsave(&clocks_lock, flags);
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mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
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& clk->pclk_sel->pclk_sel_mask;
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for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
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if (clk->pclk_sel->pclk_info[i].pclk_mask == mask)
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info = &clk->pclk_sel->pclk_info[i];
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}
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spin_unlock_irqrestore(&clocks_lock, flags);
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return info;
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}
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/*
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* Set pclk as cclk's parent and add clock sibling node to current parents
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* children list
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*/
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static void change_parent(struct clk *cclk, struct clk *pclk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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list_del(&cclk->sibling);
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list_add(&cclk->sibling, &pclk->children);
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cclk->pclk = pclk;
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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/*
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* calculates current programmed rate of pll1
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*
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* In normal mode
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* rate = (2 * M[15:8] * Fin)/(N * 2^P)
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*
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* In Dithered mode
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* rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
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*/
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void pll1_clk_recalc(struct clk *clk)
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{
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struct pll_clk_config *config = clk->private_data;
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unsigned int num = 2, den = 0, val, mode = 0;
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
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PLL_MODE_MASK;
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val = readl(config->cfg_reg);
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/* calculate denominator */
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den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
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den = 1 << den;
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den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
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/* calculate numerator & denominator */
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if (!mode) {
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/* Normal mode */
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num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
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} else {
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/* Dithered mode */
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num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
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den *= 256;
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}
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clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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/* calculates current programmed rate of ahb or apb bus */
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void bus_clk_recalc(struct clk *clk)
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{
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struct bus_clk_config *config = clk->private_data;
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unsigned int div;
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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div = ((readl(config->reg) >> config->shift) & config->mask) + 1;
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clk->rate = (unsigned long)clk->pclk->rate / div;
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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/*
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* calculates current programmed rate of auxiliary synthesizers
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* used by: UART, FIRDA
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*
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* Fout from synthesizer can be given from two equations:
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* Fout1 = (Fin * X/Y)/2
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* Fout2 = Fin * X/Y
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*
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* Selection of eqn 1 or 2 is programmed in register
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*/
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void aux_clk_recalc(struct clk *clk)
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{
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struct aux_clk_config *config = clk->private_data;
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struct pclk_info *pclk_info = NULL;
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unsigned int num = 1, den = 1, val, eqn;
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unsigned long flags;
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/* get current programmed parent */
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pclk_info = pclk_info_get(clk);
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if (!pclk_info) {
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spin_lock_irqsave(&clocks_lock, flags);
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clk->pclk = NULL;
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clk->rate = 0;
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spin_unlock_irqrestore(&clocks_lock, flags);
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return;
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}
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change_parent(clk, pclk_info->pclk);
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spin_lock_irqsave(&clocks_lock, flags);
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if (pclk_info->scalable) {
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val = readl(config->synth_reg);
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eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK;
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if (eqn == AUX_EQ1_SEL)
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den *= 2;
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/* calculate numerator */
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num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK;
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/* calculate denominator */
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den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK;
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val = (((clk->pclk->rate/10000) * num) / den) * 10000;
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} else
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val = clk->pclk->rate;
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clk->rate = val;
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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/*
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* calculates current programmed rate of gpt synthesizers
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* Fout from synthesizer can be given from below equations:
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* Fout= Fin/((2 ^ (N+1)) * (M+1))
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*/
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void gpt_clk_recalc(struct clk *clk)
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{
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struct aux_clk_config *config = clk->private_data;
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struct pclk_info *pclk_info = NULL;
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unsigned int div = 1, val;
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unsigned long flags;
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pclk_info = pclk_info_get(clk);
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if (!pclk_info) {
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spin_lock_irqsave(&clocks_lock, flags);
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clk->pclk = NULL;
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clk->rate = 0;
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spin_unlock_irqrestore(&clocks_lock, flags);
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return;
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}
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change_parent(clk, pclk_info->pclk);
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spin_lock_irqsave(&clocks_lock, flags);
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if (pclk_info->scalable) {
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val = readl(config->synth_reg);
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div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK;
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div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
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}
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clk->rate = (unsigned long)clk->pclk->rate / div;
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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/*
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* Used for clocks that always have same value as the parent clock divided by a
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* fixed divisor
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*/
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void follow_parent(struct clk *clk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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clk->rate = clk->pclk->rate;
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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/**
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* recalc_root_clocks - recalculate and propagate all root clocks
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*
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* Recalculates all root clocks (clocks with no parent), which if the
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* clock's .recalc is set correctly, should also propagate their rates.
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*/
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void recalc_root_clocks(void)
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{
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propagate_rate(&root_clks);
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}
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