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f39d01be4c
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (44 commits) vlynq: make whole Kconfig-menu dependant on architecture add descriptive comment for TIF_MEMDIE task flag declaration. EEPROM: max6875: Header file cleanup EEPROM: 93cx6: Header file cleanup EEPROM: Header file cleanup agp: use NULL instead of 0 when pointer is needed rtc-v3020: make bitfield unsigned PCI: make bitfield unsigned jbd2: use NULL instead of 0 when pointer is needed cciss: fix shadows sparse warning doc: inode uses a mutex instead of a semaphore. uml: i386: Avoid redefinition of NR_syscalls fix "seperate" typos in comments cocbalt_lcdfb: correct sections doc: Change urls for sparse Powerpc: wii: Fix typo in comment i2o: cleanup some exit paths Documentation/: it's -> its where appropriate UML: Fix compiler warning due to missing task_struct declaration UML: add kernel.h include to signal.c ...
377 lines
8.9 KiB
C
377 lines
8.9 KiB
C
/* linux/arch/arm/mach-s3c2443/clock.c
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*
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* Copyright (c) 2007, 2010 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2443 Clock control support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/sysdev.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/regs-s3c2443-clock.h>
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#include <plat/cpu-freq.h>
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#include <plat/s3c2443.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/cpu.h>
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/* We currently have to assume that the system is running
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* from the XTPll input, and that all ***REFCLKs are being
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* fed from it, as we cannot read the state of OM[4] from
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* software.
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*
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* It would be possible for each board initialisation to
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* set the correct muxing at initialisation
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*/
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/* clock selections */
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static struct clk clk_i2s_ext = {
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.name = "i2s-ext",
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.id = -1,
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};
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/* armdiv
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*
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* this clock is sourced from msysclk and can have a number of
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* divider values applied to it to then be fed into armclk.
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*/
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/* armdiv divisor table */
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static unsigned int armdiv[16] = {
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[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
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[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
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[S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
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[S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
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[S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
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[S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
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[S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
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[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
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};
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static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
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{
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clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
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return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
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}
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static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent = clk_get_rate(clk->parent);
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unsigned long calc;
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unsigned best = 256; /* bigger than any value */
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unsigned div;
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int ptr;
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for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
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div = armdiv[ptr];
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calc = parent / div;
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if (calc <= rate && div < best)
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best = div;
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}
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return parent / best;
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}
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static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
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{
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unsigned long parent = clk_get_rate(clk->parent);
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unsigned long calc;
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unsigned div;
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unsigned best = 256; /* bigger than any value */
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int ptr;
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int val = -1;
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for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
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div = armdiv[ptr];
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calc = parent / div;
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if (calc <= rate && div < best) {
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best = div;
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val = ptr;
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}
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}
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if (val >= 0) {
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unsigned long clkcon0;
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clkcon0 = __raw_readl(S3C2443_CLKDIV0);
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clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
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clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
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__raw_writel(clkcon0, S3C2443_CLKDIV0);
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}
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return (val == -1) ? -EINVAL : 0;
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}
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static struct clk clk_armdiv = {
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.name = "armdiv",
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.id = -1,
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.parent = &clk_msysclk.clk,
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.ops = &(struct clk_ops) {
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.round_rate = s3c2443_armclk_roundrate,
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.set_rate = s3c2443_armclk_setrate,
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},
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};
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/* armclk
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*
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* this is the clock fed into the ARM core itself, from armdiv or from hclk.
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*/
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static struct clk *clk_arm_sources[] = {
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[0] = &clk_armdiv,
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[1] = &clk_h,
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};
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static struct clksrc_clk clk_arm = {
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.clk = {
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.name = "armclk",
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.id = -1,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_arm_sources,
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.nr_sources = ARRAY_SIZE(clk_arm_sources),
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},
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.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
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};
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/* hsspi
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*
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* high-speed spi clock, sourced from esysclk
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*/
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static struct clksrc_clk clk_hsspi = {
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.clk = {
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.name = "hsspi",
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.id = -1,
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.parent = &clk_esysclk.clk,
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.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
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};
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/* clk_hsmcc_div
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*
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* this clock is sourced from epll, and is fed through a divider,
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* to a mux controlled by sclkcon where either it or a extclk can
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* be fed to the hsmmc block
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*/
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static struct clksrc_clk clk_hsmmc_div = {
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.clk = {
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.name = "hsmmc-div",
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.id = -1,
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
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};
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static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
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clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
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S3C2443_SCLKCON_HSMMCCLK_EPLL);
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if (parent == &clk_epll)
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clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
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else if (parent == &clk_ext)
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clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
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else
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return -EINVAL;
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if (clk->usage > 0) {
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__raw_writel(clksrc, S3C2443_SCLKCON);
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}
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clk->parent = parent;
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return 0;
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}
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static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
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{
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return s3c2443_setparent_hsmmc(clk, clk->parent);
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}
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static struct clk clk_hsmmc = {
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.name = "hsmmc-if",
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.id = -1,
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.parent = &clk_hsmmc_div.clk,
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.enable = s3c2443_enable_hsmmc,
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.ops = &(struct clk_ops) {
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.set_parent = s3c2443_setparent_hsmmc,
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},
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};
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/* i2s_eplldiv
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*
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* This clock is the output from the I2S divisor of ESYSCLK, and is separate
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* from the mux that comes after it (cannot merge into one single clock)
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*/
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static struct clksrc_clk clk_i2s_eplldiv = {
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.clk = {
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.name = "i2s-eplldiv",
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.id = -1,
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
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};
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/* i2s-ref
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*
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* i2s bus reference clock, selectable from external, esysclk or epllref
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*
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* Note, this used to be two clocks, but was compressed into one.
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*/
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struct clk *clk_i2s_srclist[] = {
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[0] = &clk_i2s_eplldiv.clk,
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[1] = &clk_i2s_ext,
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[2] = &clk_epllref.clk,
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[3] = &clk_epllref.clk,
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};
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static struct clksrc_clk clk_i2s = {
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.clk = {
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.name = "i2s-if",
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.id = -1,
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.ctrlbit = S3C2443_SCLKCON_I2SCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_i2s_srclist,
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.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
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};
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/* standard clock definitions */
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static struct clk init_clocks_off[] = {
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{
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.name = "sdi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_SDI,
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}, {
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.name = "iis",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIS,
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_SPI0,
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_SPI1,
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}
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};
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static struct clk init_clocks[] = {
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};
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/* clocks to add straight away */
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static struct clksrc_clk *clksrcs[] __initdata = {
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&clk_arm,
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&clk_i2s_eplldiv,
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&clk_i2s,
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&clk_hsspi,
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&clk_hsmmc_div,
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};
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static struct clk *clks[] __initdata = {
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&clk_hsmmc,
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&clk_armdiv,
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};
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void __init_or_cpufreq s3c2443_setup_clocks(void)
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{
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s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
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}
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void __init s3c2443_init_clocks(int xtal)
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{
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unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
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int ptr;
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clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
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clk_epll.parent = &clk_epllref.clk;
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s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
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s3c2443_setup_clocks();
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s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_register_clksrc(clksrcs[ptr], 1);
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/* register clocks from clock array */
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s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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/* We must be careful disabling the clocks we are not intending to
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* be using at boot time, as subsystems such as the LCD which do
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* their own DMA requests to the bus can cause the system to lockup
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* if they where in the middle of requesting bus access.
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*
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* Disabling the LCD clock if the LCD is active is very dangerous,
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* and therefore the bootloader should be careful to not enable
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* the LCD clock if it is not needed.
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*/
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/* install (and disable) the clocks we do not need immediately */
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_pwmclk_init();
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}
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