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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bd4fb6d270
We currently use a DSB; ISB sequence to inhibit speculation in set_fs(). Whilst this works for current CPUs, future CPUs may implement a new SB barrier instruction which acts as an architected speculation barrier. On CPUs that support it, patch in an SB; NOP sequence over the DSB; ISB sequence and advertise the presence of the new instruction to userspace. Signed-off-by: Will Deacon <will.deacon@arm.com>
62 lines
2.0 KiB
C
62 lines
2.0 KiB
C
/*
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* arch/arm64/include/asm/cpucaps.h
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*
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* Copyright (C) 2016 ARM Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CPUCAPS_H
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#define __ASM_CPUCAPS_H
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#define ARM64_WORKAROUND_CLEAN_CACHE 0
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#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
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#define ARM64_WORKAROUND_845719 2
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#define ARM64_HAS_SYSREG_GIC_CPUIF 3
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#define ARM64_HAS_PAN 4
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#define ARM64_HAS_LSE_ATOMICS 5
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#define ARM64_WORKAROUND_CAVIUM_23154 6
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#define ARM64_WORKAROUND_834220 7
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#define ARM64_HAS_NO_HW_PREFETCH 8
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#define ARM64_HAS_UAO 9
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#define ARM64_ALT_PAN_NOT_UAO 10
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#define ARM64_HAS_VIRT_HOST_EXTN 11
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#define ARM64_WORKAROUND_CAVIUM_27456 12
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#define ARM64_HAS_32BIT_EL0 13
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#define ARM64_HARDEN_EL2_VECTORS 14
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#define ARM64_HAS_CNP 15
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#define ARM64_HAS_NO_FPSIMD 16
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#define ARM64_WORKAROUND_REPEAT_TLBI 17
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#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
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#define ARM64_WORKAROUND_858921 19
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#define ARM64_WORKAROUND_CAVIUM_30115 20
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#define ARM64_HAS_DCPOP 21
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#define ARM64_SVE 22
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#define ARM64_UNMAP_KERNEL_AT_EL0 23
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#define ARM64_HARDEN_BRANCH_PREDICTOR 24
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#define ARM64_HAS_RAS_EXTN 25
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#define ARM64_WORKAROUND_843419 26
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#define ARM64_HAS_CACHE_IDC 27
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#define ARM64_HAS_CACHE_DIC 28
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#define ARM64_HW_DBM 29
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#define ARM64_SSBD 30
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#define ARM64_MISMATCHED_CACHE_TYPE 31
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#define ARM64_HAS_STAGE2_FWB 32
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#define ARM64_HAS_CRC32 33
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#define ARM64_SSBS 34
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#define ARM64_WORKAROUND_1188873 35
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#define ARM64_HAS_SB 36
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#define ARM64_NCAPS 37
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#endif /* __ASM_CPUCAPS_H */
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