Zong Li 38f5bd23de riscv: Add cache information in AUX vector ... There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf -a' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC 8 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC 8 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 32 LEVEL2_CACHE_LINESIZE 64 Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Pekka Enberg <penberg@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-09-15 18:46:08 -07:00
..
boot	riscv: Allow building with kcov coverage	2020-07-30 11:37:35 -07:00
configs	riscv: Add SiFive drivers to rv32_defconfig	2020-08-20 11:00:21 -07:00
include	riscv: Add cache information in AUX vector	2020-09-15 18:46:08 -07:00
kernel	riscv: Add cache information in AUX vector	2020-09-15 18:46:08 -07:00
lib
mm	riscv/mm/fault: Move access error check to function	2020-09-15 18:46:05 -07:00
net	bpf, riscv: Use compressed instructions in the rv64 JIT	2020-07-21 13:26:25 -07:00
Kbuild
Kconfig	RISC-V: Remove CLINT related code from timer and arch	2020-08-20 10:58:13 -07:00
Kconfig.debug
Kconfig.socs	RISC-V: Remove CLINT related code from timer and arch	2020-08-20 10:58:13 -07:00
Makefile