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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2d69fbf3d0
Commitc296d4dc13("asm-generic: fix a compilation warning") converted the various flush_*cache_* macros in asm-generic/cacheflush.h to static inline functions. This breaks RISC-V builds, since RISC-V's cacheflush.h includes the generic cacheflush.h and then undefines the macros to be overridden. Fix by copying the subset of the no-op functions that are reused from the generic cacheflush.h into the RISC-V cacheflush.h, and dropping the include of the generic cacheflush.h. Fixes:c296d4dc13("asm-generic: fix a compilation warning") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Qian Cai <cai@lca.pw> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Linus Torvalds <torvalds@linux-foundation.org>
109 lines
2.4 KiB
C
109 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CACHEFLUSH_H
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#define _ASM_RISCV_CACHEFLUSH_H
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#include <linux/mm.h>
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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/*
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* The cache doesn't need to be flushed when TLB entries change when
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* the cache is mapped to physical memory, not virtual memory
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*/
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static inline void flush_cache_all(void)
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{
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}
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static inline void flush_cache_mm(struct mm_struct *mm)
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{
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}
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static inline void flush_cache_dup_mm(struct mm_struct *mm)
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{
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}
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static inline void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start,
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unsigned long end)
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{
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}
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static inline void flush_cache_page(struct vm_area_struct *vma,
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unsigned long vmaddr,
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unsigned long pfn)
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{
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}
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static inline void flush_dcache_mmap_lock(struct address_space *mapping)
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{
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}
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static inline void flush_dcache_mmap_unlock(struct address_space *mapping)
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{
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}
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static inline void flush_icache_page(struct vm_area_struct *vma,
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struct page *page)
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{
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}
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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}
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static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
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{
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}
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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static inline void local_flush_icache_all(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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#define PG_dcache_clean PG_arch_1
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static inline void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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/*
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* RISC-V doesn't have an instruction to flush parts of the instruction cache,
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* so instead we just flush the whole thing.
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*/
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#define flush_icache_range(start, end) flush_icache_all()
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#define flush_icache_user_range(vma, pg, addr, len) flush_icache_all()
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#ifndef CONFIG_SMP
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#define flush_icache_all() local_flush_icache_all()
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#define flush_icache_mm(mm, local) flush_icache_all()
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#else /* CONFIG_SMP */
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void flush_icache_all(void);
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void flush_icache_mm(struct mm_struct *mm, bool local);
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#endif /* CONFIG_SMP */
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/*
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* Bits in sys_riscv_flush_icache()'s flags argument.
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*/
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#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
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#define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
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#endif /* _ASM_RISCV_CACHEFLUSH_H */
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