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23705adb2c
The following set of NPC registers allow the driver to configure NPC to generate different key value schemes to compare against packet payload in MCAM search. NPC_AF_INTF(0..1)_KEX_CFG NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG Currently, the AF driver populates these registers to configure the default values to address the most common use cases such as key generation for channel number + DMAC. The secure firmware stores different configuration value of these registers to enable different NPC use case along with the name for the lookup. Patch loads profile binary from secure firmware over the exiting CGX mailbox interface and apply the profile. AF driver shall fall back to the default configuration in case of any errors. The AF consumer driver can know the selected profile on response to NPC_GET_KEX_CFG mailbox by introducing mkex_pfl_name in the struct npc_get_kex_cfg_rsp. Signed-off-by: Vamsi Attunuru <vamsi.attunuru@marvell.com> Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTx2 CGX driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef CGX_H
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#define CGX_H
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#include "mbox.h"
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#include "cgx_fw_if.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_CGX 0xA059
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/* PCI BAR nos */
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#define PCI_CFG_REG_BAR_NUM 0
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#define CGX_ID_MASK 0x7
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#define MAX_LMAC_PER_CGX 4
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#define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */
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#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)
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/* Registers */
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#define CGXX_CMRX_CFG 0x00
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#define CMR_EN BIT_ULL(55)
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#define DATA_PKT_TX_EN BIT_ULL(53)
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#define DATA_PKT_RX_EN BIT_ULL(54)
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#define CGX_LMAC_TYPE_SHIFT 40
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#define CGX_LMAC_TYPE_MASK 0xF
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#define CGXX_CMRX_INT 0x040
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#define FW_CGX_INT BIT_ULL(1)
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#define CGXX_CMRX_INT_ENA_W1S 0x058
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#define CGXX_CMRX_RX_ID_MAP 0x060
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#define CGXX_CMRX_RX_STAT0 0x070
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#define CGXX_CMRX_RX_LMACS 0x128
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#define CGXX_CMRX_RX_DMAC_CTL0 0x1F8
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#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
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#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
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#define CGX_DMAC_MCAST_MODE BIT_ULL(1)
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#define CGX_DMAC_BCAST_MODE BIT_ULL(0)
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#define CGXX_CMRX_RX_DMAC_CAM0 0x200
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#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
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#define CGXX_CMRX_RX_DMAC_CAM1 0x400
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#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
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#define CGXX_CMRX_TX_STAT0 0x700
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#define CGXX_SCRATCH0_REG 0x1050
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#define CGXX_SCRATCH1_REG 0x1058
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#define CGX_CONST 0x2000
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#define CGXX_SPUX_CONTROL1 0x10000
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#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
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#define CGXX_GMP_PCS_MRX_CTL 0x30000
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#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)
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#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
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#define CGX_EVENT_REG CGXX_SCRATCH0_REG
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#define CGX_CMD_TIMEOUT 2200 /* msecs */
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#define CGX_NVEC 37
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#define CGX_LMAC_FWI 0
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enum LMAC_TYPE {
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LMAC_MODE_SGMII = 0,
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LMAC_MODE_XAUI = 1,
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LMAC_MODE_RXAUI = 2,
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LMAC_MODE_10G_R = 3,
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LMAC_MODE_40G_R = 4,
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LMAC_MODE_QSGMII = 6,
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LMAC_MODE_25G_R = 7,
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LMAC_MODE_50G_R = 8,
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LMAC_MODE_100G_R = 9,
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LMAC_MODE_USXGMII = 10,
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LMAC_MODE_MAX,
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};
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struct cgx_link_event {
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struct cgx_link_user_info link_uinfo;
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u8 cgx_id;
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u8 lmac_id;
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};
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/**
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* struct cgx_event_cb
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* @notify_link_chg: callback for link change notification
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* @data: data passed to callback function
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*/
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struct cgx_event_cb {
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int (*notify_link_chg)(struct cgx_link_event *event, void *data);
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void *data;
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};
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extern struct pci_driver cgx_driver;
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int cgx_get_cgxcnt_max(void);
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int cgx_get_lmac_cnt(void *cgxd);
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void *cgx_get_pdata(int cgx_id);
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int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
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int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
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int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
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int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
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int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
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int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
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int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
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u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
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void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
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int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
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int cgx_get_link_info(void *cgxd, int lmac_id,
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struct cgx_link_user_info *linfo);
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int cgx_lmac_linkup_start(void *cgxd);
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int cgx_get_mkex_prfl_info(u64 *addr, u64 *size);
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#endif /* CGX_H */
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