mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 20:45:20 +07:00
381081ffc2
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2 SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver. We'll also need to support the SoC specific clock types, thus we're adding CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in the overridden cpg_clk_register() method; then, finally, add the SD-IF module clock (derived from the SD0 clock). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
/*
|
|
* R-Car Gen3 Clock Pulse Generator
|
|
*
|
|
* Copyright (C) 2015-2018 Glider bvba
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*/
|
|
|
|
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
|
#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
|
|
|
enum rcar_gen3_clk_types {
|
|
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
|
|
CLK_TYPE_GEN3_PLL0,
|
|
CLK_TYPE_GEN3_PLL1,
|
|
CLK_TYPE_GEN3_PLL2,
|
|
CLK_TYPE_GEN3_PLL3,
|
|
CLK_TYPE_GEN3_PLL4,
|
|
CLK_TYPE_GEN3_SD,
|
|
CLK_TYPE_GEN3_R,
|
|
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
|
|
CLK_TYPE_GEN3_Z,
|
|
CLK_TYPE_GEN3_Z2,
|
|
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
|
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
|
|
|
/* SoC specific definitions start here */
|
|
CLK_TYPE_GEN3_SOC_BASE,
|
|
};
|
|
|
|
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
|
|
|
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
|
|
(_parent0) << 16 | (_parent1), \
|
|
.div = (_div0) << 16 | (_div1), .offset = _md)
|
|
|
|
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
|
|
_div_clean) \
|
|
DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
|
|
_parent_clean, _div_clean)
|
|
|
|
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
|
|
|
|
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
|
|
(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
|
|
|
|
struct rcar_gen3_cpg_pll_config {
|
|
u8 extal_div;
|
|
u8 pll1_mult;
|
|
u8 pll1_div;
|
|
u8 pll3_mult;
|
|
u8 pll3_div;
|
|
u8 osc_prediv;
|
|
};
|
|
|
|
#define CPG_RCKCR 0x240
|
|
|
|
struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
|
|
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
|
struct clk **clks, void __iomem *base,
|
|
struct raw_notifier_head *notifiers);
|
|
int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
|
|
unsigned int clk_extalr, u32 mode);
|
|
|
|
#endif
|