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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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424c33830f
Add emulation for some basic MMIO registers used in the ITS emulation.
This includes:
- GITS_{CTLR,TYPER,IIDR}
- ID registers
- GITS_{CBASER,CREADR,CWRITER}
(which implement the ITS command buffer handling)
- GITS_BASER<n>
Most of the handlers are pretty straight forward, only the CWRITER
handler is a bit more involved by taking the new its_cmd mutex and
then iterating over the command buffer.
The registers holding base addresses and attributes are sanitised before
storing them.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
174 lines
5.5 KiB
C
174 lines
5.5 KiB
C
/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __KVM_ARM_VGIC_MMIO_H__
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#define __KVM_ARM_VGIC_MMIO_H__
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struct vgic_register_region {
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unsigned int reg_offset;
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unsigned int len;
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unsigned int bits_per_irq;
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unsigned int access_flags;
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union {
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unsigned long (*read)(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len);
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unsigned long (*its_read)(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len);
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};
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union {
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void (*write)(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val);
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void (*its_write)(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val);
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};
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};
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extern struct kvm_io_device_ops kvm_io_gic_ops;
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#define VGIC_ACCESS_8bit 1
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#define VGIC_ACCESS_32bit 2
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#define VGIC_ACCESS_64bit 4
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/*
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* Generate a mask that covers the number of bytes required to address
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* up to 1024 interrupts, each represented by <bits> bits. This assumes
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* that <bits> is a power of two.
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*/
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#define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1)
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/*
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* (addr & mask) gives us the byte offset for the INT ID, so we want to
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* divide this with 'bytes per irq' to get the INT ID, which is given
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* by '(bits) / 8'. But we do this with fixed-point-arithmetic and
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* take advantage of the fact that division by a fraction equals
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* multiplication with the inverted fraction, and scale up both the
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* numerator and denominator with 8 to support at most 64 bits per IRQ:
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*/
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#define VGIC_ADDR_TO_INTID(addr, bits) (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \
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64 / (bits) / 8)
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/*
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* Some VGIC registers store per-IRQ information, with a different number
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* of bits per IRQ. For those registers this macro is used.
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* The _WITH_LENGTH version instantiates registers with a fixed length
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* and is mutually exclusive with the _PER_IRQ version.
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*/
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#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = bpi, \
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.len = bpi * 1024 / 8, \
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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}
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#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = 0, \
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.len = length, \
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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}
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int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
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struct vgic_register_region *reg_desc,
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struct vgic_io_device *region,
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int nr_irqs, bool offset_private);
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unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
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void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
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unsigned long data);
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unsigned long extract_bytes(unsigned long data, unsigned int offset,
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unsigned int num);
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u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
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unsigned long val);
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unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val);
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unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
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unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
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#ifdef CONFIG_KVM_ARM_VGIC_V3
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u64 vgic_sanitise_outer_cacheability(u64 reg);
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u64 vgic_sanitise_inner_cacheability(u64 reg);
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u64 vgic_sanitise_shareability(u64 reg);
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u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
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u64 (*sanitise_fn)(u64));
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#endif
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#endif
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