mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 10:55:15 +07:00
f0fba2ad1b
This patch extends the ASoC API to allow sound cards to have more than one
CODEC and more than one platform DMA controller. This is achieved by dividing
some current ASoC structures that contain both driver data and device data into
structures that only either contain device data or driver data. i.e.
struct snd_soc_codec ---> struct snd_soc_codec (device data)
+-> struct snd_soc_codec_driver (driver data)
struct snd_soc_platform ---> struct snd_soc_platform (device data)
+-> struct snd_soc_platform_driver (driver data)
struct snd_soc_dai ---> struct snd_soc_dai (device data)
+-> struct snd_soc_dai_driver (driver data)
struct snd_soc_device ---> deleted
This now allows ASoC to be more tightly aligned with the Linux driver model and
also means that every ASoC codec, platform and (platform) DAI is a kernel
device. ASoC component private data is now stored as device private data.
The ASoC sound card struct snd_soc_card has also been updated to store lists
of it's components rather than a pointer to a codec and platform. The PCM
runtime struct soc_pcm_runtime now has pointers to all its components.
This patch adds DAPM support for ASoC multi-component and removes struct
snd_soc_socdev from DAPM core. All DAPM calls are now made on a card, codec
or runtime PCM level basis rather than using snd_soc_socdev.
Other notable multi-component changes:-
* Stream operations now de-reference less structures.
* close_delayed work() now runs on a DAI basis rather than looping all DAIs
in a card.
* PM suspend()/resume() operations can now handle N CODECs and Platforms
per sound card.
* Added soc_bind_dai_link() to bind the component devices to the sound card.
* Added soc_dai_link_probe() and soc_dai_link_remove() to probe and remove
DAI link components.
* sysfs entries can now be registered per component per card.
* snd_soc_new_pcms() functionailty rolled into dai_link_probe().
* snd_soc_register_codec() now does all the codec list and mutex init.
This patch changes the probe() and remove() of the CODEC drivers as follows:-
o Make CODEC driver a platform driver
o Moved all struct snd_soc_codec list, mutex, etc initialiasation to core.
o Removed all static codec pointers (drivers now support > 1 codec dev)
o snd_soc_register_pcms() now done by core.
o snd_soc_register_dai() folded into snd_soc_register_codec().
CS4270 portions:
Acked-by: Timur Tabi <timur@freescale.com>
Some TLV320aic23 and Cirrus platform fixes.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
TI CODEC and OMAP fixes
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Samsung platform and misc fixes :-
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
MPC8610 and PPC fixes.
Signed-off-by: Timur Tabi <timur@freescale.com>
i.MX fixes and some core fixes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
J4740 platform fixes:-
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
CC: Tony Lindgren <tony@atomide.com>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Kevin Hilman <khilman@deeprootsystems.com>
CC: Sascha Hauer <s.hauer@pengutronix.de>
CC: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
CC: Kuninori Morimoto <morimoto.kuninori@renesas.com>
CC: Daniel Gloeckner <dg@emlix.com>
CC: Manuel Lauss <mano@roarinelk.homelinux.net>
CC: Mike Frysinger <vapier.adi@gmail.com>
CC: Arnaud Patard <apatard@mandriva.com>
CC: Wan ZongShun <mcuos.com@gmail.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
836 lines
35 KiB
C
836 lines
35 KiB
C
/*
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* wm8990.h -- audio driver for WM8990
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*
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* Copyright 2007 Wolfson Microelectronics PLC.
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* Author: Graeme Gregory
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* graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __WM8990REGISTERDEFS_H__
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#define __WM8990REGISTERDEFS_H__
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/*
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* Register values.
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*/
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#define WM8990_RESET 0x00
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#define WM8990_POWER_MANAGEMENT_1 0x01
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#define WM8990_POWER_MANAGEMENT_2 0x02
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#define WM8990_POWER_MANAGEMENT_3 0x03
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#define WM8990_AUDIO_INTERFACE_1 0x04
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#define WM8990_AUDIO_INTERFACE_2 0x05
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#define WM8990_CLOCKING_1 0x06
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#define WM8990_CLOCKING_2 0x07
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#define WM8990_AUDIO_INTERFACE_3 0x08
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#define WM8990_AUDIO_INTERFACE_4 0x09
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#define WM8990_DAC_CTRL 0x0A
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#define WM8990_LEFT_DAC_DIGITAL_VOLUME 0x0B
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#define WM8990_RIGHT_DAC_DIGITAL_VOLUME 0x0C
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#define WM8990_DIGITAL_SIDE_TONE 0x0D
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#define WM8990_ADC_CTRL 0x0E
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#define WM8990_LEFT_ADC_DIGITAL_VOLUME 0x0F
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#define WM8990_RIGHT_ADC_DIGITAL_VOLUME 0x10
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#define WM8990_GPIO_CTRL_1 0x12
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#define WM8990_GPIO1_GPIO2 0x13
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#define WM8990_GPIO3_GPIO4 0x14
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#define WM8990_GPIO5_GPIO6 0x15
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#define WM8990_GPIOCTRL_2 0x16
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#define WM8990_GPIO_POL 0x17
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#define WM8990_LEFT_LINE_INPUT_1_2_VOLUME 0x18
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#define WM8990_LEFT_LINE_INPUT_3_4_VOLUME 0x19
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#define WM8990_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
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#define WM8990_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
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#define WM8990_LEFT_OUTPUT_VOLUME 0x1C
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#define WM8990_RIGHT_OUTPUT_VOLUME 0x1D
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#define WM8990_LINE_OUTPUTS_VOLUME 0x1E
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#define WM8990_OUT3_4_VOLUME 0x1F
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#define WM8990_LEFT_OPGA_VOLUME 0x20
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#define WM8990_RIGHT_OPGA_VOLUME 0x21
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#define WM8990_SPEAKER_VOLUME 0x22
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#define WM8990_CLASSD1 0x23
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#define WM8990_CLASSD3 0x25
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#define WM8990_CLASSD4 0x26
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#define WM8990_INPUT_MIXER1 0x27
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#define WM8990_INPUT_MIXER2 0x28
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#define WM8990_INPUT_MIXER3 0x29
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#define WM8990_INPUT_MIXER4 0x2A
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#define WM8990_INPUT_MIXER5 0x2B
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#define WM8990_INPUT_MIXER6 0x2C
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#define WM8990_OUTPUT_MIXER1 0x2D
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#define WM8990_OUTPUT_MIXER2 0x2E
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#define WM8990_OUTPUT_MIXER3 0x2F
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#define WM8990_OUTPUT_MIXER4 0x30
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#define WM8990_OUTPUT_MIXER5 0x31
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#define WM8990_OUTPUT_MIXER6 0x32
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#define WM8990_OUT3_4_MIXER 0x33
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#define WM8990_LINE_MIXER1 0x34
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#define WM8990_LINE_MIXER2 0x35
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#define WM8990_SPEAKER_MIXER 0x36
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#define WM8990_ADDITIONAL_CONTROL 0x37
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#define WM8990_ANTIPOP1 0x38
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#define WM8990_ANTIPOP2 0x39
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#define WM8990_MICBIAS 0x3A
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#define WM8990_PLL1 0x3C
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#define WM8990_PLL2 0x3D
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#define WM8990_PLL3 0x3E
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#define WM8990_INTDRIVBITS 0x3F
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#define WM8990_EXT_ACCESS_ENA 0x75
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#define WM8990_EXT_CTL1 0x7a
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/*
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* Field Definitions.
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*/
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/*
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* R0 (0x00) - Reset
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*/
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#define WM8990_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID */
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/*
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* R1 (0x01) - Power Management (1)
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*/
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#define WM8990_SPK_ENA 0x1000 /* SPK_ENA */
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#define WM8990_SPK_ENA_BIT 12
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#define WM8990_OUT3_ENA 0x0800 /* OUT3_ENA */
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#define WM8990_OUT3_ENA_BIT 11
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#define WM8990_OUT4_ENA 0x0400 /* OUT4_ENA */
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#define WM8990_OUT4_ENA_BIT 10
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#define WM8990_LOUT_ENA 0x0200 /* LOUT_ENA */
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#define WM8990_LOUT_ENA_BIT 9
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#define WM8990_ROUT_ENA 0x0100 /* ROUT_ENA */
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#define WM8990_ROUT_ENA_BIT 8
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#define WM8990_MICBIAS_ENA 0x0010 /* MICBIAS_ENA */
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#define WM8990_MICBIAS_ENA_BIT 4
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#define WM8990_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
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#define WM8990_VREF_ENA 0x0001 /* VREF_ENA */
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#define WM8990_VREF_ENA_BIT 0
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/*
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* R2 (0x02) - Power Management (2)
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*/
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#define WM8990_PLL_ENA 0x8000 /* PLL_ENA */
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#define WM8990_PLL_ENA_BIT 15
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#define WM8990_TSHUT_ENA 0x4000 /* TSHUT_ENA */
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#define WM8990_TSHUT_ENA_BIT 14
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#define WM8990_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
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#define WM8990_TSHUT_OPDIS_BIT 13
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#define WM8990_OPCLK_ENA 0x0800 /* OPCLK_ENA */
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#define WM8990_OPCLK_ENA_BIT 11
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#define WM8990_AINL_ENA 0x0200 /* AINL_ENA */
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#define WM8990_AINL_ENA_BIT 9
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#define WM8990_AINR_ENA 0x0100 /* AINR_ENA */
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#define WM8990_AINR_ENA_BIT 8
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#define WM8990_LIN34_ENA 0x0080 /* LIN34_ENA */
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#define WM8990_LIN34_ENA_BIT 7
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#define WM8990_LIN12_ENA 0x0040 /* LIN12_ENA */
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#define WM8990_LIN12_ENA_BIT 6
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#define WM8990_RIN34_ENA 0x0020 /* RIN34_ENA */
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#define WM8990_RIN34_ENA_BIT 5
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#define WM8990_RIN12_ENA 0x0010 /* RIN12_ENA */
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#define WM8990_RIN12_ENA_BIT 4
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#define WM8990_ADCL_ENA 0x0002 /* ADCL_ENA */
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#define WM8990_ADCL_ENA_BIT 1
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#define WM8990_ADCR_ENA 0x0001 /* ADCR_ENA */
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#define WM8990_ADCR_ENA_BIT 0
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/*
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* R3 (0x03) - Power Management (3)
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*/
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#define WM8990_LON_ENA 0x2000 /* LON_ENA */
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#define WM8990_LON_ENA_BIT 13
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#define WM8990_LOP_ENA 0x1000 /* LOP_ENA */
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#define WM8990_LOP_ENA_BIT 12
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#define WM8990_RON_ENA 0x0800 /* RON_ENA */
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#define WM8990_RON_ENA_BIT 11
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#define WM8990_ROP_ENA 0x0400 /* ROP_ENA */
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#define WM8990_ROP_ENA_BIT 10
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#define WM8990_LOPGA_ENA 0x0080 /* LOPGA_ENA */
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#define WM8990_LOPGA_ENA_BIT 7
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#define WM8990_ROPGA_ENA 0x0040 /* ROPGA_ENA */
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#define WM8990_ROPGA_ENA_BIT 6
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#define WM8990_LOMIX_ENA 0x0020 /* LOMIX_ENA */
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#define WM8990_LOMIX_ENA_BIT 5
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#define WM8990_ROMIX_ENA 0x0010 /* ROMIX_ENA */
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#define WM8990_ROMIX_ENA_BIT 4
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#define WM8990_DACL_ENA 0x0002 /* DACL_ENA */
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#define WM8990_DACL_ENA_BIT 1
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#define WM8990_DACR_ENA 0x0001 /* DACR_ENA */
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#define WM8990_DACR_ENA_BIT 0
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/*
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* R4 (0x04) - Audio Interface (1)
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*/
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#define WM8990_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
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#define WM8990_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
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#define WM8990_AIFADC_TDM 0x2000 /* AIFADC_TDM */
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#define WM8990_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
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#define WM8990_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
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#define WM8990_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
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#define WM8990_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
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#define WM8990_AIF_WL_16BITS (0 << 5)
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#define WM8990_AIF_WL_20BITS (1 << 5)
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#define WM8990_AIF_WL_24BITS (2 << 5)
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#define WM8990_AIF_WL_32BITS (3 << 5)
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#define WM8990_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
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#define WM8990_AIF_TMF_RIGHTJ (0 << 3)
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#define WM8990_AIF_TMF_LEFTJ (1 << 3)
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#define WM8990_AIF_TMF_I2S (2 << 3)
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#define WM8990_AIF_TMF_DSP (3 << 3)
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/*
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* R5 (0x05) - Audio Interface (2)
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*/
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#define WM8990_DACL_SRC 0x8000 /* DACL_SRC */
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#define WM8990_DACR_SRC 0x4000 /* DACR_SRC */
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#define WM8990_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
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#define WM8990_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
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#define WM8990_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST */
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#define WM8990_DAC_COMP 0x0010 /* DAC_COMP */
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#define WM8990_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
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#define WM8990_ADC_COMP 0x0004 /* ADC_COMP */
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#define WM8990_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
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#define WM8990_LOOPBACK 0x0001 /* LOOPBACK */
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/*
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* R6 (0x06) - Clocking (1)
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*/
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#define WM8990_TOCLK_RATE 0x8000 /* TOCLK_RATE */
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#define WM8990_TOCLK_ENA 0x4000 /* TOCLK_ENA */
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#define WM8990_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
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#define WM8990_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
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#define WM8990_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
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#define WM8990_BCLK_DIV_1 (0x0 << 1)
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#define WM8990_BCLK_DIV_1_5 (0x1 << 1)
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#define WM8990_BCLK_DIV_2 (0x2 << 1)
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#define WM8990_BCLK_DIV_3 (0x3 << 1)
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#define WM8990_BCLK_DIV_4 (0x4 << 1)
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#define WM8990_BCLK_DIV_5_5 (0x5 << 1)
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#define WM8990_BCLK_DIV_6 (0x6 << 1)
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#define WM8990_BCLK_DIV_8 (0x7 << 1)
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#define WM8990_BCLK_DIV_11 (0x8 << 1)
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#define WM8990_BCLK_DIV_12 (0x9 << 1)
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#define WM8990_BCLK_DIV_16 (0xA << 1)
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#define WM8990_BCLK_DIV_22 (0xB << 1)
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#define WM8990_BCLK_DIV_24 (0xC << 1)
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#define WM8990_BCLK_DIV_32 (0xD << 1)
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#define WM8990_BCLK_DIV_44 (0xE << 1)
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#define WM8990_BCLK_DIV_48 (0xF << 1)
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/*
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* R7 (0x07) - Clocking (2)
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*/
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#define WM8990_MCLK_SRC 0x8000 /* MCLK_SRC */
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#define WM8990_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
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#define WM8990_CLK_FORCE 0x2000 /* CLK_FORCE */
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#define WM8990_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
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#define WM8990_MCLK_DIV_1 (0 << 11)
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#define WM8990_MCLK_DIV_2 (2 << 11)
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#define WM8990_MCLK_INV 0x0400 /* MCLK_INV */
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#define WM8990_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV */
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#define WM8990_ADC_CLKDIV_1 (0 << 5)
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#define WM8990_ADC_CLKDIV_1_5 (1 << 5)
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#define WM8990_ADC_CLKDIV_2 (2 << 5)
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#define WM8990_ADC_CLKDIV_3 (3 << 5)
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#define WM8990_ADC_CLKDIV_4 (4 << 5)
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#define WM8990_ADC_CLKDIV_5_5 (5 << 5)
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#define WM8990_ADC_CLKDIV_6 (6 << 5)
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#define WM8990_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
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#define WM8990_DAC_CLKDIV_1 (0 << 2)
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#define WM8990_DAC_CLKDIV_1_5 (1 << 2)
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#define WM8990_DAC_CLKDIV_2 (2 << 2)
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#define WM8990_DAC_CLKDIV_3 (3 << 2)
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#define WM8990_DAC_CLKDIV_4 (4 << 2)
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#define WM8990_DAC_CLKDIV_5_5 (5 << 2)
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#define WM8990_DAC_CLKDIV_6 (6 << 2)
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/*
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* R8 (0x08) - Audio Interface (3)
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*/
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#define WM8990_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
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#define WM8990_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
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#define WM8990_AIF_SEL 0x2000 /* AIF_SEL */
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#define WM8990_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
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#define WM8990_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE */
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/*
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* R9 (0x09) - Audio Interface (4)
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*/
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#define WM8990_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
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#define WM8990_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
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#define WM8990_AIF_TRIS 0x2000 /* AIF_TRIS */
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#define WM8990_DACLRC_DIR 0x0800 /* DACLRC_DIR */
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#define WM8990_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE */
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/*
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* R10 (0x0A) - DAC CTRL
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*/
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#define WM8990_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
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#define WM8990_DAC_MONO 0x0200 /* DAC_MONO */
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#define WM8990_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */
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#define WM8990_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */
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#define WM8990_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */
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#define WM8990_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */
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#define WM8990_DAC_MUTE 0x0004 /* DAC_MUTE */
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#define WM8990_DACL_DATINV 0x0002 /* DACL_DATINV */
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#define WM8990_DACR_DATINV 0x0001 /* DACR_DATINV */
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/*
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* R11 (0x0B) - Left DAC Digital Volume
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*/
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#define WM8990_DAC_VU 0x0100 /* DAC_VU */
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#define WM8990_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
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#define WM8990_DACL_VOL_SHIFT 0
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/*
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* R12 (0x0C) - Right DAC Digital Volume
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*/
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#define WM8990_DAC_VU 0x0100 /* DAC_VU */
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#define WM8990_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
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#define WM8990_DACR_VOL_SHIFT 0
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/*
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* R13 (0x0D) - Digital Side Tone
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*/
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#define WM8990_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL */
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#define WM8990_ADCL_DAC_SVOL_SHIFT 9
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#define WM8990_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL */
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#define WM8990_ADCR_DAC_SVOL_SHIFT 5
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#define WM8990_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */
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#define WM8990_ADC_TO_DACL_SHIFT 2
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#define WM8990_ADC_TO_DACR_MASK 0x03 /* ADC_TO_DACR - [1:0] */
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#define WM8990_ADC_TO_DACR_SHIFT 0
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/*
|
|
* R14 (0x0E) - ADC CTRL
|
|
*/
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#define WM8990_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */
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#define WM8990_ADC_HPF_ENA_BIT 8
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#define WM8990_ADC_HPF_CUT_MASK 0x03 /* ADC_HPF_CUT - [6:5] */
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#define WM8990_ADC_HPF_CUT_SHIFT 5
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#define WM8990_ADCL_DATINV 0x0002 /* ADCL_DATINV */
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#define WM8990_ADCL_DATINV_BIT 1
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#define WM8990_ADCR_DATINV 0x0001 /* ADCR_DATINV */
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#define WM8990_ADCR_DATINV_BIT 0
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/*
|
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* R15 (0x0F) - Left ADC Digital Volume
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|
*/
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#define WM8990_ADC_VU 0x0100 /* ADC_VU */
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#define WM8990_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
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#define WM8990_ADCL_VOL_SHIFT 0
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/*
|
|
* R16 (0x10) - Right ADC Digital Volume
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|
*/
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#define WM8990_ADC_VU 0x0100 /* ADC_VU */
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#define WM8990_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
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#define WM8990_ADCR_VOL_SHIFT 0
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/*
|
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* R18 (0x12) - GPIO CTRL 1
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*/
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#define WM8990_IRQ 0x1000 /* IRQ */
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#define WM8990_TEMPOK 0x0800 /* TEMPOK */
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#define WM8990_MICSHRT 0x0400 /* MICSHRT */
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#define WM8990_MICDET 0x0200 /* MICDET */
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#define WM8990_PLL_LCK 0x0100 /* PLL_LCK */
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#define WM8990_GPI8_STATUS 0x0080 /* GPI8_STATUS */
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#define WM8990_GPI7_STATUS 0x0040 /* GPI7_STATUS */
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#define WM8990_GPIO6_STATUS 0x0020 /* GPIO6_STATUS */
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#define WM8990_GPIO5_STATUS 0x0010 /* GPIO5_STATUS */
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#define WM8990_GPIO4_STATUS 0x0008 /* GPIO4_STATUS */
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#define WM8990_GPIO3_STATUS 0x0004 /* GPIO3_STATUS */
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#define WM8990_GPIO2_STATUS 0x0002 /* GPIO2_STATUS */
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#define WM8990_GPIO1_STATUS 0x0001 /* GPIO1_STATUS */
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/*
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* R19 (0x13) - GPIO1 & GPIO2
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*/
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#define WM8990_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
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#define WM8990_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
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#define WM8990_GPIO2_PU 0x2000 /* GPIO2_PU */
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#define WM8990_GPIO2_PD 0x1000 /* GPIO2_PD */
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#define WM8990_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
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#define WM8990_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
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#define WM8990_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
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#define WM8990_GPIO1_PU 0x0020 /* GPIO1_PU */
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#define WM8990_GPIO1_PD 0x0010 /* GPIO1_PD */
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#define WM8990_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
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/*
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* R20 (0x14) - GPIO3 & GPIO4
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|
*/
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#define WM8990_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
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#define WM8990_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
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#define WM8990_GPIO4_PU 0x2000 /* GPIO4_PU */
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#define WM8990_GPIO4_PD 0x1000 /* GPIO4_PD */
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#define WM8990_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
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#define WM8990_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
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#define WM8990_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
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#define WM8990_GPIO3_PU 0x0020 /* GPIO3_PU */
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#define WM8990_GPIO3_PD 0x0010 /* GPIO3_PD */
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#define WM8990_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
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|
|
|
/*
|
|
* R21 (0x15) - GPIO5 & GPIO6
|
|
*/
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#define WM8990_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
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#define WM8990_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
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#define WM8990_GPIO6_PU 0x2000 /* GPIO6_PU */
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#define WM8990_GPIO6_PD 0x1000 /* GPIO6_PD */
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#define WM8990_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
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#define WM8990_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
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#define WM8990_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
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#define WM8990_GPIO5_PU 0x0020 /* GPIO5_PU */
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#define WM8990_GPIO5_PD 0x0010 /* GPIO5_PD */
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#define WM8990_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
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|
|
|
/*
|
|
* R22 (0x16) - GPIOCTRL 2
|
|
*/
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|
#define WM8990_RD_3W_ENA 0x8000 /* RD_3W_ENA */
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|
#define WM8990_MODE_3W4W 0x4000 /* MODE_3W4W */
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|
#define WM8990_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
|
|
#define WM8990_MICSHRT_IRQ_ENA 0x0400 /* MICSHRT_IRQ_ENA */
|
|
#define WM8990_MICDET_IRQ_ENA 0x0200 /* MICDET_IRQ_ENA */
|
|
#define WM8990_PLL_LCK_IRQ_ENA 0x0100 /* PLL_LCK_IRQ_ENA */
|
|
#define WM8990_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
|
|
#define WM8990_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
|
|
#define WM8990_GPI8_ENA 0x0010 /* GPI8_ENA */
|
|
#define WM8990_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
|
|
#define WM8990_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
|
|
#define WM8990_GPI7_ENA 0x0001 /* GPI7_ENA */
|
|
|
|
/*
|
|
* R23 (0x17) - GPIO_POL
|
|
*/
|
|
#define WM8990_IRQ_INV 0x1000 /* IRQ_INV */
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|
#define WM8990_TEMPOK_POL 0x0800 /* TEMPOK_POL */
|
|
#define WM8990_MICSHRT_POL 0x0400 /* MICSHRT_POL */
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|
#define WM8990_MICDET_POL 0x0200 /* MICDET_POL */
|
|
#define WM8990_PLL_LCK_POL 0x0100 /* PLL_LCK_POL */
|
|
#define WM8990_GPI8_POL 0x0080 /* GPI8_POL */
|
|
#define WM8990_GPI7_POL 0x0040 /* GPI7_POL */
|
|
#define WM8990_GPIO6_POL 0x0020 /* GPIO6_POL */
|
|
#define WM8990_GPIO5_POL 0x0010 /* GPIO5_POL */
|
|
#define WM8990_GPIO4_POL 0x0008 /* GPIO4_POL */
|
|
#define WM8990_GPIO3_POL 0x0004 /* GPIO3_POL */
|
|
#define WM8990_GPIO2_POL 0x0002 /* GPIO2_POL */
|
|
#define WM8990_GPIO1_POL 0x0001 /* GPIO1_POL */
|
|
|
|
/*
|
|
* R24 (0x18) - Left Line Input 1&2 Volume
|
|
*/
|
|
#define WM8990_IPVU 0x0100 /* IPVU */
|
|
#define WM8990_LI12MUTE 0x0080 /* LI12MUTE */
|
|
#define WM8990_LI12MUTE_BIT 7
|
|
#define WM8990_LI12ZC 0x0040 /* LI12ZC */
|
|
#define WM8990_LI12ZC_BIT 6
|
|
#define WM8990_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */
|
|
#define WM8990_LIN12VOL_SHIFT 0
|
|
/*
|
|
* R25 (0x19) - Left Line Input 3&4 Volume
|
|
*/
|
|
#define WM8990_IPVU 0x0100 /* IPVU */
|
|
#define WM8990_LI34MUTE 0x0080 /* LI34MUTE */
|
|
#define WM8990_LI34MUTE_BIT 7
|
|
#define WM8990_LI34ZC 0x0040 /* LI34ZC */
|
|
#define WM8990_LI34ZC_BIT 6
|
|
#define WM8990_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */
|
|
#define WM8990_LIN34VOL_SHIFT 0
|
|
|
|
/*
|
|
* R26 (0x1A) - Right Line Input 1&2 Volume
|
|
*/
|
|
#define WM8990_IPVU 0x0100 /* IPVU */
|
|
#define WM8990_RI12MUTE 0x0080 /* RI12MUTE */
|
|
#define WM8990_RI12MUTE_BIT 7
|
|
#define WM8990_RI12ZC 0x0040 /* RI12ZC */
|
|
#define WM8990_RI12ZC_BIT 6
|
|
#define WM8990_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */
|
|
#define WM8990_RIN12VOL_SHIFT 0
|
|
|
|
/*
|
|
* R27 (0x1B) - Right Line Input 3&4 Volume
|
|
*/
|
|
#define WM8990_IPVU 0x0100 /* IPVU */
|
|
#define WM8990_RI34MUTE 0x0080 /* RI34MUTE */
|
|
#define WM8990_RI34MUTE_BIT 7
|
|
#define WM8990_RI34ZC 0x0040 /* RI34ZC */
|
|
#define WM8990_RI34ZC_BIT 6
|
|
#define WM8990_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */
|
|
#define WM8990_RIN34VOL_SHIFT 0
|
|
|
|
/*
|
|
* R28 (0x1C) - Left Output Volume
|
|
*/
|
|
#define WM8990_OPVU 0x0100 /* OPVU */
|
|
#define WM8990_LOZC 0x0080 /* LOZC */
|
|
#define WM8990_LOZC_BIT 7
|
|
#define WM8990_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */
|
|
#define WM8990_LOUTVOL_SHIFT 0
|
|
/*
|
|
* R29 (0x1D) - Right Output Volume
|
|
*/
|
|
#define WM8990_OPVU 0x0100 /* OPVU */
|
|
#define WM8990_ROZC 0x0080 /* ROZC */
|
|
#define WM8990_ROZC_BIT 7
|
|
#define WM8990_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */
|
|
#define WM8990_ROUTVOL_SHIFT 0
|
|
/*
|
|
* R30 (0x1E) - Line Outputs Volume
|
|
*/
|
|
#define WM8990_LONMUTE 0x0040 /* LONMUTE */
|
|
#define WM8990_LONMUTE_BIT 6
|
|
#define WM8990_LOPMUTE 0x0020 /* LOPMUTE */
|
|
#define WM8990_LOPMUTE_BIT 5
|
|
#define WM8990_LOATTN 0x0010 /* LOATTN */
|
|
#define WM8990_LOATTN_BIT 4
|
|
#define WM8990_RONMUTE 0x0004 /* RONMUTE */
|
|
#define WM8990_RONMUTE_BIT 2
|
|
#define WM8990_ROPMUTE 0x0002 /* ROPMUTE */
|
|
#define WM8990_ROPMUTE_BIT 1
|
|
#define WM8990_ROATTN 0x0001 /* ROATTN */
|
|
#define WM8990_ROATTN_BIT 0
|
|
|
|
/*
|
|
* R31 (0x1F) - Out3/4 Volume
|
|
*/
|
|
#define WM8990_OUT3MUTE 0x0020 /* OUT3MUTE */
|
|
#define WM8990_OUT3MUTE_BIT 5
|
|
#define WM8990_OUT3ATTN 0x0010 /* OUT3ATTN */
|
|
#define WM8990_OUT3ATTN_BIT 4
|
|
#define WM8990_OUT4MUTE 0x0002 /* OUT4MUTE */
|
|
#define WM8990_OUT4MUTE_BIT 1
|
|
#define WM8990_OUT4ATTN 0x0001 /* OUT4ATTN */
|
|
#define WM8990_OUT4ATTN_BIT 0
|
|
|
|
/*
|
|
* R32 (0x20) - Left OPGA Volume
|
|
*/
|
|
#define WM8990_OPVU 0x0100 /* OPVU */
|
|
#define WM8990_LOPGAZC 0x0080 /* LOPGAZC */
|
|
#define WM8990_LOPGAZC_BIT 7
|
|
#define WM8990_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */
|
|
#define WM8990_LOPGAVOL_SHIFT 0
|
|
|
|
/*
|
|
* R33 (0x21) - Right OPGA Volume
|
|
*/
|
|
#define WM8990_OPVU 0x0100 /* OPVU */
|
|
#define WM8990_ROPGAZC 0x0080 /* ROPGAZC */
|
|
#define WM8990_ROPGAZC_BIT 7
|
|
#define WM8990_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */
|
|
#define WM8990_ROPGAVOL_SHIFT 0
|
|
/*
|
|
* R34 (0x22) - Speaker Volume
|
|
*/
|
|
#define WM8990_SPKATTN_MASK 0x0003 /* SPKATTN - [1:0] */
|
|
#define WM8990_SPKATTN_SHIFT 0
|
|
|
|
/*
|
|
* R35 (0x23) - ClassD1
|
|
*/
|
|
#define WM8990_CDMODE 0x0100 /* CDMODE */
|
|
#define WM8990_CDMODE_BIT 8
|
|
|
|
/*
|
|
* R37 (0x25) - ClassD3
|
|
*/
|
|
#define WM8990_DCGAIN_MASK 0x0007 /* DCGAIN - [5:3] */
|
|
#define WM8990_DCGAIN_SHIFT 3
|
|
#define WM8990_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */
|
|
#define WM8990_ACGAIN_SHIFT 0
|
|
|
|
/*
|
|
* R38 (0x26) - ClassD4
|
|
*/
|
|
#define WM8990_SPKZC_MASK 0x0001 /* SPKZC */
|
|
#define WM8990_SPKZC_SHIFT 7 /* SPKZC */
|
|
#define WM8990_SPKVOL_MASK 0x007F /* SPKVOL - [6:0] */
|
|
#define WM8990_SPKVOL_SHIFT 0 /* SPKVOL - [6:0] */
|
|
|
|
/*
|
|
* R39 (0x27) - Input Mixer1
|
|
*/
|
|
#define WM8990_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */
|
|
#define WM8990_AINLMODE_SHIFT 2
|
|
#define WM8990_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */
|
|
#define WM8990_AINRMODE_SHIFT 0
|
|
|
|
/*
|
|
* R40 (0x28) - Input Mixer2
|
|
*/
|
|
#define WM8990_LMP4 0x0080 /* LMP4 */
|
|
#define WM8990_LMP4_BIT 7 /* LMP4 */
|
|
#define WM8990_LMN3 0x0040 /* LMN3 */
|
|
#define WM8990_LMN3_BIT 6 /* LMN3 */
|
|
#define WM8990_LMP2 0x0020 /* LMP2 */
|
|
#define WM8990_LMP2_BIT 5 /* LMP2 */
|
|
#define WM8990_LMN1 0x0010 /* LMN1 */
|
|
#define WM8990_LMN1_BIT 4 /* LMN1 */
|
|
#define WM8990_RMP4 0x0008 /* RMP4 */
|
|
#define WM8990_RMP4_BIT 3 /* RMP4 */
|
|
#define WM8990_RMN3 0x0004 /* RMN3 */
|
|
#define WM8990_RMN3_BIT 2 /* RMN3 */
|
|
#define WM8990_RMP2 0x0002 /* RMP2 */
|
|
#define WM8990_RMP2_BIT 1 /* RMP2 */
|
|
#define WM8990_RMN1 0x0001 /* RMN1 */
|
|
#define WM8990_RMN1_BIT 0 /* RMN1 */
|
|
|
|
/*
|
|
* R41 (0x29) - Input Mixer3
|
|
*/
|
|
#define WM8990_L34MNB 0x0100 /* L34MNB */
|
|
#define WM8990_L34MNB_BIT 8
|
|
#define WM8990_L34MNBST 0x0080 /* L34MNBST */
|
|
#define WM8990_L34MNBST_BIT 7
|
|
#define WM8990_L12MNB 0x0020 /* L12MNB */
|
|
#define WM8990_L12MNB_BIT 5
|
|
#define WM8990_L12MNBST 0x0010 /* L12MNBST */
|
|
#define WM8990_L12MNBST_BIT 4
|
|
#define WM8990_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */
|
|
#define WM8990_LDBVOL_SHIFT 0
|
|
|
|
/*
|
|
* R42 (0x2A) - Input Mixer4
|
|
*/
|
|
#define WM8990_R34MNB 0x0100 /* R34MNB */
|
|
#define WM8990_R34MNB_BIT 8
|
|
#define WM8990_R34MNBST 0x0080 /* R34MNBST */
|
|
#define WM8990_R34MNBST_BIT 7
|
|
#define WM8990_R12MNB 0x0020 /* R12MNB */
|
|
#define WM8990_R12MNB_BIT 5
|
|
#define WM8990_R12MNBST 0x0010 /* R12MNBST */
|
|
#define WM8990_R12MNBST_BIT 4
|
|
#define WM8990_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */
|
|
#define WM8990_RDBVOL_SHIFT 0
|
|
|
|
/*
|
|
* R43 (0x2B) - Input Mixer5
|
|
*/
|
|
#define WM8990_LI2BVOL_MASK 0x07 /* LI2BVOL - [8:6] */
|
|
#define WM8990_LI2BVOL_SHIFT 6
|
|
#define WM8990_LR4BVOL_MASK 0x07 /* LR4BVOL - [5:3] */
|
|
#define WM8990_LR4BVOL_SHIFT 3
|
|
#define WM8990_LL4BVOL_MASK 0x07 /* LL4BVOL - [2:0] */
|
|
#define WM8990_LL4BVOL_SHIFT 0
|
|
|
|
/*
|
|
* R44 (0x2C) - Input Mixer6
|
|
*/
|
|
#define WM8990_RI2BVOL_MASK 0x07 /* RI2BVOL - [8:6] */
|
|
#define WM8990_RI2BVOL_SHIFT 6
|
|
#define WM8990_RL4BVOL_MASK 0x07 /* RL4BVOL - [5:3] */
|
|
#define WM8990_RL4BVOL_SHIFT 3
|
|
#define WM8990_RR4BVOL_MASK 0x07 /* RR4BVOL - [2:0] */
|
|
#define WM8990_RR4BVOL_SHIFT 0
|
|
|
|
/*
|
|
* R45 (0x2D) - Output Mixer1
|
|
*/
|
|
#define WM8990_LRBLO 0x0080 /* LRBLO */
|
|
#define WM8990_LRBLO_BIT 7
|
|
#define WM8990_LLBLO 0x0040 /* LLBLO */
|
|
#define WM8990_LLBLO_BIT 6
|
|
#define WM8990_LRI3LO 0x0020 /* LRI3LO */
|
|
#define WM8990_LRI3LO_BIT 5
|
|
#define WM8990_LLI3LO 0x0010 /* LLI3LO */
|
|
#define WM8990_LLI3LO_BIT 4
|
|
#define WM8990_LR12LO 0x0008 /* LR12LO */
|
|
#define WM8990_LR12LO_BIT 3
|
|
#define WM8990_LL12LO 0x0004 /* LL12LO */
|
|
#define WM8990_LL12LO_BIT 2
|
|
#define WM8990_LDLO 0x0001 /* LDLO */
|
|
#define WM8990_LDLO_BIT 0
|
|
|
|
/*
|
|
* R46 (0x2E) - Output Mixer2
|
|
*/
|
|
#define WM8990_RLBRO 0x0080 /* RLBRO */
|
|
#define WM8990_RLBRO_BIT 7
|
|
#define WM8990_RRBRO 0x0040 /* RRBRO */
|
|
#define WM8990_RRBRO_BIT 6
|
|
#define WM8990_RLI3RO 0x0020 /* RLI3RO */
|
|
#define WM8990_RLI3RO_BIT 5
|
|
#define WM8990_RRI3RO 0x0010 /* RRI3RO */
|
|
#define WM8990_RRI3RO_BIT 4
|
|
#define WM8990_RL12RO 0x0008 /* RL12RO */
|
|
#define WM8990_RL12RO_BIT 3
|
|
#define WM8990_RR12RO 0x0004 /* RR12RO */
|
|
#define WM8990_RR12RO_BIT 2
|
|
#define WM8990_RDRO 0x0001 /* RDRO */
|
|
#define WM8990_RDRO_BIT 0
|
|
|
|
/*
|
|
* R47 (0x2F) - Output Mixer3
|
|
*/
|
|
#define WM8990_LLI3LOVOL_MASK 0x07 /* LLI3LOVOL - [8:6] */
|
|
#define WM8990_LLI3LOVOL_SHIFT 6
|
|
#define WM8990_LR12LOVOL_MASK 0x07 /* LR12LOVOL - [5:3] */
|
|
#define WM8990_LR12LOVOL_SHIFT 3
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|
#define WM8990_LL12LOVOL_MASK 0x07 /* LL12LOVOL - [2:0] */
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#define WM8990_LL12LOVOL_SHIFT 0
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/*
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* R48 (0x30) - Output Mixer4
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*/
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#define WM8990_RRI3ROVOL_MASK 0x07 /* RRI3ROVOL - [8:6] */
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#define WM8990_RRI3ROVOL_SHIFT 6
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#define WM8990_RL12ROVOL_MASK 0x07 /* RL12ROVOL - [5:3] */
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#define WM8990_RL12ROVOL_SHIFT 3
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#define WM8990_RR12ROVOL_MASK 0x07 /* RR12ROVOL - [2:0] */
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#define WM8990_RR12ROVOL_SHIFT 0
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/*
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* R49 (0x31) - Output Mixer5
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*/
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#define WM8990_LRI3LOVOL_MASK 0x07 /* LRI3LOVOL - [8:6] */
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#define WM8990_LRI3LOVOL_SHIFT 6
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#define WM8990_LRBLOVOL_MASK 0x07 /* LRBLOVOL - [5:3] */
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#define WM8990_LRBLOVOL_SHIFT 3
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#define WM8990_LLBLOVOL_MASK 0x07 /* LLBLOVOL - [2:0] */
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#define WM8990_LLBLOVOL_SHIFT 0
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/*
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* R50 (0x32) - Output Mixer6
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*/
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#define WM8990_RLI3ROVOL_MASK 0x07 /* RLI3ROVOL - [8:6] */
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#define WM8990_RLI3ROVOL_SHIFT 6
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#define WM8990_RLBROVOL_MASK 0x07 /* RLBROVOL - [5:3] */
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#define WM8990_RLBROVOL_SHIFT 3
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#define WM8990_RRBROVOL_MASK 0x07 /* RRBROVOL - [2:0] */
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#define WM8990_RRBROVOL_SHIFT 0
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/*
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* R51 (0x33) - Out3/4 Mixer
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*/
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#define WM8990_VSEL_MASK 0x0180 /* VSEL - [8:7] */
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#define WM8990_LI4O3 0x0020 /* LI4O3 */
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#define WM8990_LI4O3_BIT 5
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#define WM8990_LPGAO3 0x0010 /* LPGAO3 */
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#define WM8990_LPGAO3_BIT 4
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#define WM8990_RI4O4 0x0002 /* RI4O4 */
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#define WM8990_RI4O4_BIT 1
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#define WM8990_RPGAO4 0x0001 /* RPGAO4 */
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#define WM8990_RPGAO4_BIT 0
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/*
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* R52 (0x34) - Line Mixer1
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*/
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#define WM8990_LLOPGALON 0x0040 /* LLOPGALON */
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#define WM8990_LLOPGALON_BIT 6
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#define WM8990_LROPGALON 0x0020 /* LROPGALON */
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#define WM8990_LROPGALON_BIT 5
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#define WM8990_LOPLON 0x0010 /* LOPLON */
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#define WM8990_LOPLON_BIT 4
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#define WM8990_LR12LOP 0x0004 /* LR12LOP */
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#define WM8990_LR12LOP_BIT 2
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#define WM8990_LL12LOP 0x0002 /* LL12LOP */
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#define WM8990_LL12LOP_BIT 1
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#define WM8990_LLOPGALOP 0x0001 /* LLOPGALOP */
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#define WM8990_LLOPGALOP_BIT 0
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/*
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* R53 (0x35) - Line Mixer2
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*/
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#define WM8990_RROPGARON 0x0040 /* RROPGARON */
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#define WM8990_RROPGARON_BIT 6
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#define WM8990_RLOPGARON 0x0020 /* RLOPGARON */
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#define WM8990_RLOPGARON_BIT 5
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#define WM8990_ROPRON 0x0010 /* ROPRON */
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#define WM8990_ROPRON_BIT 4
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#define WM8990_RL12ROP 0x0004 /* RL12ROP */
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#define WM8990_RL12ROP_BIT 2
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#define WM8990_RR12ROP 0x0002 /* RR12ROP */
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#define WM8990_RR12ROP_BIT 1
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#define WM8990_RROPGAROP 0x0001 /* RROPGAROP */
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#define WM8990_RROPGAROP_BIT 0
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/*
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* R54 (0x36) - Speaker Mixer
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*/
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#define WM8990_LB2SPK 0x0080 /* LB2SPK */
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#define WM8990_LB2SPK_BIT 7
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#define WM8990_RB2SPK 0x0040 /* RB2SPK */
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#define WM8990_RB2SPK_BIT 6
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#define WM8990_LI2SPK 0x0020 /* LI2SPK */
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#define WM8990_LI2SPK_BIT 5
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#define WM8990_RI2SPK 0x0010 /* RI2SPK */
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#define WM8990_RI2SPK_BIT 4
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#define WM8990_LOPGASPK 0x0008 /* LOPGASPK */
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#define WM8990_LOPGASPK_BIT 3
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#define WM8990_ROPGASPK 0x0004 /* ROPGASPK */
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#define WM8990_ROPGASPK_BIT 2
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#define WM8990_LDSPK 0x0002 /* LDSPK */
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#define WM8990_LDSPK_BIT 1
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#define WM8990_RDSPK 0x0001 /* RDSPK */
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#define WM8990_RDSPK_BIT 0
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/*
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* R55 (0x37) - Additional Control
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*/
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#define WM8990_VROI 0x0001 /* VROI */
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/*
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* R56 (0x38) - AntiPOP1
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*/
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#define WM8990_DIS_LLINE 0x0020 /* DIS_LLINE */
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#define WM8990_DIS_RLINE 0x0010 /* DIS_RLINE */
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#define WM8990_DIS_OUT3 0x0008 /* DIS_OUT3 */
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#define WM8990_DIS_OUT4 0x0004 /* DIS_OUT4 */
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#define WM8990_DIS_LOUT 0x0002 /* DIS_LOUT */
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#define WM8990_DIS_ROUT 0x0001 /* DIS_ROUT */
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/*
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* R57 (0x39) - AntiPOP2
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|
*/
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#define WM8990_SOFTST 0x0040 /* SOFTST */
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#define WM8990_BUFIOEN 0x0008 /* BUFIOEN */
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#define WM8990_BUFDCOPEN 0x0004 /* BUFDCOPEN */
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#define WM8990_POBCTRL 0x0002 /* POBCTRL */
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#define WM8990_VMIDTOG 0x0001 /* VMIDTOG */
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/*
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* R58 (0x3A) - MICBIAS
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*/
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#define WM8990_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */
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#define WM8990_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */
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#define WM8990_MCD 0x0004 /* MCD */
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#define WM8990_MBSEL 0x0001 /* MBSEL */
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/*
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* R60 (0x3C) - PLL1
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|
*/
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#define WM8990_SDM 0x0080 /* SDM */
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#define WM8990_PRESCALE 0x0040 /* PRESCALE */
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#define WM8990_PLLN_MASK 0x000F /* PLLN - [3:0] */
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/*
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* R61 (0x3D) - PLL2
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|
*/
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#define WM8990_PLLK1_MASK 0x00FF /* PLLK1 - [7:0] */
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/*
|
|
* R62 (0x3E) - PLL3
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|
*/
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|
#define WM8990_PLLK2_MASK 0x00FF /* PLLK2 - [7:0] */
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/*
|
|
* R63 (0x3F) - Internal Driver Bits
|
|
*/
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|
#define WM8990_INMIXL_PWR_BIT 0
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|
#define WM8990_AINLMUX_PWR_BIT 1
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#define WM8990_INMIXR_PWR_BIT 2
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|
#define WM8990_AINRMUX_PWR_BIT 3
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#define WM8990_MCLK_DIV 0
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|
#define WM8990_DACCLK_DIV 1
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#define WM8990_ADCCLK_DIV 2
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|
#define WM8990_BCLK_DIV 3
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|
|
|
#endif /* __WM8990REGISTERDEFS_H__ */
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/*------------------------------ END OF FILE ---------------------------------*/
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