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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8c33de98fe
Signed-off-by: Stephen George <Stephen.George@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
129 lines
3.5 KiB
Plaintext
129 lines
3.5 KiB
Plaintext
/*
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* T4240 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/include/ "e6500_power_isa.dtsi"
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/ {
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compatible = "fsl,T4240";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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ccsr = &soc;
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dcsr = &dcsr;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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crypto = &crypto;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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pci3 = &pci3;
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dma0 = &dma0;
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dma1 = &dma1;
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sdhc = &sdhc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,e6500@0 {
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device_type = "cpu";
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reg = <0 1>;
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next-level-cache = <&L2_1>;
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};
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cpu1: PowerPC,e6500@1 {
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device_type = "cpu";
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reg = <2 3>;
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next-level-cache = <&L2_1>;
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};
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cpu2: PowerPC,e6500@2 {
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device_type = "cpu";
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reg = <4 5>;
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next-level-cache = <&L2_1>;
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};
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cpu3: PowerPC,e6500@3 {
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device_type = "cpu";
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reg = <6 7>;
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next-level-cache = <&L2_1>;
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};
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cpu4: PowerPC,e6500@4 {
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device_type = "cpu";
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reg = <8 9>;
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next-level-cache = <&L2_2>;
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};
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cpu5: PowerPC,e6500@5 {
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device_type = "cpu";
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reg = <10 11>;
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next-level-cache = <&L2_2>;
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};
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cpu6: PowerPC,e6500@6 {
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device_type = "cpu";
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reg = <12 13>;
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next-level-cache = <&L2_2>;
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};
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cpu7: PowerPC,e6500@7 {
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device_type = "cpu";
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reg = <14 15>;
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next-level-cache = <&L2_2>;
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};
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cpu8: PowerPC,e6500@8 {
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device_type = "cpu";
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reg = <16 17>;
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next-level-cache = <&L2_3>;
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};
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cpu9: PowerPC,e6500@9 {
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device_type = "cpu";
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reg = <18 19>;
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next-level-cache = <&L2_3>;
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};
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cpu10: PowerPC,e6500@10 {
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device_type = "cpu";
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reg = <20 21>;
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next-level-cache = <&L2_3>;
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};
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cpu11: PowerPC,e6500@11 {
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device_type = "cpu";
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reg = <22 23>;
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next-level-cache = <&L2_3>;
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};
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};
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};
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