mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
37e5bf6535
The clock rate was assumed to be static but it actually changes depending on the mode of operation, correct this to help improve the calcuation of the listenTime for ANI. This change will help adjust ANI more accurately on different PHY thresholds. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
690 lines
19 KiB
C
690 lines
19 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "hw-ops.h"
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static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
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if (ah->ani[i].c &&
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ah->ani[i].c->channel == chan->channel)
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return i;
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if (ah->ani[i].c == NULL) {
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ah->ani[i].c = chan;
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return i;
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}
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}
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ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
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"No more channel states left. Using channel 0\n");
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return 0;
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}
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static void ath9k_hw_update_mibstats(struct ath_hw *ah,
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struct ath9k_mib_stats *stats)
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{
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stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
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stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
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stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
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stats->rts_good += REG_READ(ah, AR_RTS_OK);
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stats->beacons += REG_READ(ah, AR_BEACON_CNT);
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}
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static void ath9k_ani_restart(struct ath_hw *ah)
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{
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struct ar5416AniState *aniState;
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struct ath_common *common = ath9k_hw_common(ah);
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if (!DO_ANI(ah))
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return;
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aniState = ah->curani;
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aniState->listenTime = 0;
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if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
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aniState->ofdmPhyErrBase = 0;
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ath_print(common, ATH_DBG_ANI,
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"OFDM Trigger is too high for hw counters\n");
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} else {
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aniState->ofdmPhyErrBase =
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AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
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}
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if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
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aniState->cckPhyErrBase = 0;
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ath_print(common, ATH_DBG_ANI,
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"CCK Trigger is too high for hw counters\n");
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} else {
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aniState->cckPhyErrBase =
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AR_PHY_COUNTMAX - aniState->cckTrigHigh;
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}
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ath_print(common, ATH_DBG_ANI,
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"Writing ofdmbase=%u cckbase=%u\n",
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aniState->ofdmPhyErrBase,
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aniState->cckPhyErrBase);
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ENABLE_REGWRITE_BUFFER(ah);
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REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
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REGWRITE_BUFFER_FLUSH(ah);
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DISABLE_REGWRITE_BUFFER(ah);
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
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aniState->ofdmPhyErrCount = 0;
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aniState->cckPhyErrCount = 0;
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}
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static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
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{
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struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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struct ar5416AniState *aniState;
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int32_t rssi;
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if (!DO_ANI(ah))
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return;
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aniState = ah->curani;
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if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
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aniState->noiseImmunityLevel + 1)) {
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return;
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}
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}
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if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
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aniState->spurImmunityLevel + 1)) {
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return;
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}
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}
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if (ah->opmode == NL80211_IFTYPE_AP) {
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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}
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return;
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}
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rssi = BEACON_RSSI(ah);
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if (rssi > aniState->rssiThrHigh) {
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if (!aniState->ofdmWeakSigDetectOff) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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false)) {
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
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return;
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}
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}
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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return;
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}
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} else if (rssi > aniState->rssiThrLow) {
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if (aniState->ofdmWeakSigDetectOff)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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true);
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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return;
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} else {
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if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
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!conf_is_ht(conf)) {
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if (!aniState->ofdmWeakSigDetectOff)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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false);
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if (aniState->firstepLevel > 0)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL, 0);
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return;
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}
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}
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}
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static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
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{
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struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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struct ar5416AniState *aniState;
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int32_t rssi;
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if (!DO_ANI(ah))
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return;
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aniState = ah->curani;
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if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
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aniState->noiseImmunityLevel + 1)) {
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return;
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}
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}
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if (ah->opmode == NL80211_IFTYPE_AP) {
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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}
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return;
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}
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rssi = BEACON_RSSI(ah);
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if (rssi > aniState->rssiThrLow) {
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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} else {
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if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
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!conf_is_ht(conf)) {
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if (aniState->firstepLevel > 0)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL, 0);
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}
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}
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}
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static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
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{
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struct ar5416AniState *aniState;
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int32_t rssi;
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aniState = ah->curani;
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if (ah->opmode == NL80211_IFTYPE_AP) {
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if (aniState->firstepLevel > 0) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel - 1))
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return;
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}
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} else {
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rssi = BEACON_RSSI(ah);
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if (rssi > aniState->rssiThrHigh) {
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/* XXX: Handle me */
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} else if (rssi > aniState->rssiThrLow) {
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if (aniState->ofdmWeakSigDetectOff) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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true) == true)
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return;
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}
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if (aniState->firstepLevel > 0) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel - 1) == true)
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return;
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}
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} else {
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if (aniState->firstepLevel > 0) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel - 1) == true)
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return;
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}
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}
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}
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if (aniState->spurImmunityLevel > 0) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
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aniState->spurImmunityLevel - 1))
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return;
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}
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if (aniState->noiseImmunityLevel > 0) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
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aniState->noiseImmunityLevel - 1);
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return;
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}
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}
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static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
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{
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struct ath9k_channel *chan = ah->curchan;
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struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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u8 clockrate; /* in MHz */
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if (!ah->curchan) /* should really check for CCK instead */
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clockrate = ATH9K_CLOCK_RATE_CCK;
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else if (conf->channel->band == IEEE80211_BAND_2GHZ)
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clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
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else if (IS_CHAN_A_FAST_CLOCK(ah, chan))
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clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
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else
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clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
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if (conf_is_ht40(conf))
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return clockrate * 2;
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return clockrate * 2;
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}
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static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
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{
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struct ar5416AniState *aniState;
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u32 txFrameCount, rxFrameCount, cycleCount;
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int32_t listenTime;
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txFrameCount = REG_READ(ah, AR_TFCNT);
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rxFrameCount = REG_READ(ah, AR_RFCNT);
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cycleCount = REG_READ(ah, AR_CCCNT);
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aniState = ah->curani;
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if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
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listenTime = 0;
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ah->stats.ast_ani_lzero++;
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} else {
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int32_t ccdelta = cycleCount - aniState->cycleCount;
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int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
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int32_t tfdelta = txFrameCount - aniState->txFrameCount;
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int32_t clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
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/*
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* convert HW counter values to ms using mode
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* specifix clock rate
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*/
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clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
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listenTime = (ccdelta - rfdelta - tfdelta) / clock_rate;
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}
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aniState->cycleCount = cycleCount;
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aniState->txFrameCount = txFrameCount;
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aniState->rxFrameCount = rxFrameCount;
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return listenTime;
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}
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void ath9k_ani_reset(struct ath_hw *ah)
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{
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struct ar5416AniState *aniState;
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struct ath9k_channel *chan = ah->curchan;
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struct ath_common *common = ath9k_hw_common(ah);
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int index;
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if (!DO_ANI(ah))
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return;
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index = ath9k_hw_get_ani_channel_idx(ah, chan);
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aniState = &ah->ani[index];
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ah->curani = aniState;
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if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
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&& ah->opmode != NL80211_IFTYPE_ADHOC) {
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ath_print(common, ATH_DBG_ANI,
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"Reset ANI state opmode %u\n", ah->opmode);
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ah->stats.ast_ani_reset++;
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if (ah->opmode == NL80211_IFTYPE_AP) {
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/*
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* ath9k_hw_ani_control() will only process items set on
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* ah->ani_function
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*/
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if (IS_CHAN_2GHZ(chan))
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ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
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ATH9K_ANI_FIRSTEP_LEVEL);
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else
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ah->ani_function = 0;
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}
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ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
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ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
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ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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!ATH9K_ANI_USE_OFDM_WEAK_SIG);
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ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
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ATH9K_ANI_CCK_WEAK_SIG_THR);
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ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
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ATH9K_RX_FILTER_PHYERR);
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if (ah->opmode == NL80211_IFTYPE_AP) {
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ah->curani->ofdmTrigHigh =
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ah->config.ofdm_trig_high;
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ah->curani->ofdmTrigLow =
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ah->config.ofdm_trig_low;
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ah->curani->cckTrigHigh =
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ah->config.cck_trig_high;
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ah->curani->cckTrigLow =
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ah->config.cck_trig_low;
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}
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ath9k_ani_restart(ah);
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return;
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}
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if (aniState->noiseImmunityLevel != 0)
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ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
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aniState->noiseImmunityLevel);
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if (aniState->spurImmunityLevel != 0)
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ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
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aniState->spurImmunityLevel);
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if (aniState->ofdmWeakSigDetectOff)
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ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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!aniState->ofdmWeakSigDetectOff);
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if (aniState->cckWeakSigThreshold)
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ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
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aniState->cckWeakSigThreshold);
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if (aniState->firstepLevel != 0)
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel);
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ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
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~ATH9K_RX_FILTER_PHYERR);
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ath9k_ani_restart(ah);
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ENABLE_REGWRITE_BUFFER(ah);
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REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
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REGWRITE_BUFFER_FLUSH(ah);
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DISABLE_REGWRITE_BUFFER(ah);
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}
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void ath9k_hw_ani_monitor(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ar5416AniState *aniState;
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struct ath_common *common = ath9k_hw_common(ah);
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int32_t listenTime;
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u32 phyCnt1, phyCnt2;
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u32 ofdmPhyErrCnt, cckPhyErrCnt;
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if (!DO_ANI(ah))
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return;
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aniState = ah->curani;
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listenTime = ath9k_hw_ani_get_listen_time(ah);
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if (listenTime < 0) {
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ah->stats.ast_ani_lneg++;
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ath9k_ani_restart(ah);
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return;
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}
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aniState->listenTime += listenTime;
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
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phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
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phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
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if (phyCnt1 < aniState->ofdmPhyErrBase ||
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phyCnt2 < aniState->cckPhyErrBase) {
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if (phyCnt1 < aniState->ofdmPhyErrBase) {
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ath_print(common, ATH_DBG_ANI,
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"phyCnt1 0x%x, resetting "
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"counter value to 0x%x\n",
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phyCnt1,
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aniState->ofdmPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_1,
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aniState->ofdmPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_MASK_1,
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AR_PHY_ERR_OFDM_TIMING);
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}
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if (phyCnt2 < aniState->cckPhyErrBase) {
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ath_print(common, ATH_DBG_ANI,
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"phyCnt2 0x%x, resetting "
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"counter value to 0x%x\n",
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phyCnt2,
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aniState->cckPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_2,
|
|
aniState->cckPhyErrBase);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_2,
|
|
AR_PHY_ERR_CCK_TIMING);
|
|
}
|
|
return;
|
|
}
|
|
|
|
ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
|
|
ah->stats.ast_ani_ofdmerrs +=
|
|
ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
|
|
aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
|
|
|
|
cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
|
|
ah->stats.ast_ani_cckerrs +=
|
|
cckPhyErrCnt - aniState->cckPhyErrCount;
|
|
aniState->cckPhyErrCount = cckPhyErrCnt;
|
|
|
|
if (aniState->listenTime > 5 * ah->aniperiod) {
|
|
if (aniState->ofdmPhyErrCount <= aniState->listenTime *
|
|
aniState->ofdmTrigLow / 1000 &&
|
|
aniState->cckPhyErrCount <= aniState->listenTime *
|
|
aniState->cckTrigLow / 1000)
|
|
ath9k_hw_ani_lower_immunity(ah);
|
|
ath9k_ani_restart(ah);
|
|
} else if (aniState->listenTime > ah->aniperiod) {
|
|
if (aniState->ofdmPhyErrCount > aniState->listenTime *
|
|
aniState->ofdmTrigHigh / 1000) {
|
|
ath9k_hw_ani_ofdm_err_trigger(ah);
|
|
ath9k_ani_restart(ah);
|
|
} else if (aniState->cckPhyErrCount >
|
|
aniState->listenTime * aniState->cckTrigHigh /
|
|
1000) {
|
|
ath9k_hw_ani_cck_err_trigger(ah);
|
|
ath9k_ani_restart(ah);
|
|
}
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_ani_monitor);
|
|
|
|
void ath9k_enable_mib_counters(struct ath_hw *ah)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
|
|
|
|
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
|
|
|
|
ENABLE_REGWRITE_BUFFER(ah);
|
|
|
|
REG_WRITE(ah, AR_FILT_OFDM, 0);
|
|
REG_WRITE(ah, AR_FILT_CCK, 0);
|
|
REG_WRITE(ah, AR_MIBC,
|
|
~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
|
|
& 0x0f);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
|
|
|
REGWRITE_BUFFER_FLUSH(ah);
|
|
DISABLE_REGWRITE_BUFFER(ah);
|
|
}
|
|
|
|
/* Freeze the MIB counters, get the stats and then clear them */
|
|
void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
|
|
|
|
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
|
|
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
|
|
REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
|
|
REG_WRITE(ah, AR_FILT_OFDM, 0);
|
|
REG_WRITE(ah, AR_FILT_CCK, 0);
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
|
|
|
|
u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
|
|
u32 *rxc_pcnt,
|
|
u32 *rxf_pcnt,
|
|
u32 *txf_pcnt)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
static u32 cycles, rx_clear, rx_frame, tx_frame;
|
|
u32 good = 1;
|
|
|
|
u32 rc = REG_READ(ah, AR_RCCNT);
|
|
u32 rf = REG_READ(ah, AR_RFCNT);
|
|
u32 tf = REG_READ(ah, AR_TFCNT);
|
|
u32 cc = REG_READ(ah, AR_CCCNT);
|
|
|
|
if (cycles == 0 || cycles > cc) {
|
|
ath_print(common, ATH_DBG_ANI,
|
|
"cycle counter wrap. ExtBusy = 0\n");
|
|
good = 0;
|
|
} else {
|
|
u32 cc_d = cc - cycles;
|
|
u32 rc_d = rc - rx_clear;
|
|
u32 rf_d = rf - rx_frame;
|
|
u32 tf_d = tf - tx_frame;
|
|
|
|
if (cc_d != 0) {
|
|
*rxc_pcnt = rc_d * 100 / cc_d;
|
|
*rxf_pcnt = rf_d * 100 / cc_d;
|
|
*txf_pcnt = tf_d * 100 / cc_d;
|
|
} else {
|
|
good = 0;
|
|
}
|
|
}
|
|
|
|
cycles = cc;
|
|
rx_frame = rf;
|
|
rx_clear = rc;
|
|
tx_frame = tf;
|
|
|
|
return good;
|
|
}
|
|
|
|
/*
|
|
* Process a MIB interrupt. We may potentially be invoked because
|
|
* any of the MIB counters overflow/trigger so don't assume we're
|
|
* here because a PHY error counter triggered.
|
|
*/
|
|
void ath9k_hw_procmibevent(struct ath_hw *ah)
|
|
{
|
|
u32 phyCnt1, phyCnt2;
|
|
|
|
/* Reset these counters regardless */
|
|
REG_WRITE(ah, AR_FILT_OFDM, 0);
|
|
REG_WRITE(ah, AR_FILT_CCK, 0);
|
|
if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
|
|
REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
|
|
|
|
/* Clear the mib counters and save them in the stats */
|
|
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
|
|
|
|
if (!DO_ANI(ah))
|
|
return;
|
|
|
|
/* NB: these are not reset-on-read */
|
|
phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
|
|
phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
|
|
if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
|
|
((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
|
|
struct ar5416AniState *aniState = ah->curani;
|
|
u32 ofdmPhyErrCnt, cckPhyErrCnt;
|
|
|
|
/* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
|
|
ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
|
|
ah->stats.ast_ani_ofdmerrs +=
|
|
ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
|
|
aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
|
|
|
|
cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
|
|
ah->stats.ast_ani_cckerrs +=
|
|
cckPhyErrCnt - aniState->cckPhyErrCount;
|
|
aniState->cckPhyErrCount = cckPhyErrCnt;
|
|
|
|
/*
|
|
* NB: figure out which counter triggered. If both
|
|
* trigger we'll only deal with one as the processing
|
|
* clobbers the error counter so the trigger threshold
|
|
* check will never be true.
|
|
*/
|
|
if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
|
|
ath9k_hw_ani_ofdm_err_trigger(ah);
|
|
if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
|
|
ath9k_hw_ani_cck_err_trigger(ah);
|
|
/* NB: always restart to insure the h/w counters are reset */
|
|
ath9k_ani_restart(ah);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_procmibevent);
|
|
|
|
void ath9k_hw_ani_setup(struct ath_hw *ah)
|
|
{
|
|
int i;
|
|
|
|
const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
|
|
const int coarseHigh[] = { -14, -14, -14, -14, -12 };
|
|
const int coarseLow[] = { -64, -64, -64, -64, -70 };
|
|
const int firpwr[] = { -78, -78, -78, -78, -80 };
|
|
|
|
for (i = 0; i < 5; i++) {
|
|
ah->totalSizeDesired[i] = totalSizeDesired[i];
|
|
ah->coarse_high[i] = coarseHigh[i];
|
|
ah->coarse_low[i] = coarseLow[i];
|
|
ah->firpwr[i] = firpwr[i];
|
|
}
|
|
}
|
|
|
|
void ath9k_hw_ani_init(struct ath_hw *ah)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
int i;
|
|
|
|
ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
|
|
|
|
memset(ah->ani, 0, sizeof(ah->ani));
|
|
for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
|
|
ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
|
|
ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
|
|
ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
|
|
ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
|
|
ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
|
|
ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
|
|
ah->ani[i].ofdmWeakSigDetectOff =
|
|
!ATH9K_ANI_USE_OFDM_WEAK_SIG;
|
|
ah->ani[i].cckWeakSigThreshold =
|
|
ATH9K_ANI_CCK_WEAK_SIG_THR;
|
|
ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
|
|
ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
|
|
ah->ani[i].ofdmPhyErrBase =
|
|
AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
|
|
ah->ani[i].cckPhyErrBase =
|
|
AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
|
|
}
|
|
|
|
ath_print(common, ATH_DBG_ANI,
|
|
"Setting OfdmErrBase = 0x%08x\n",
|
|
ah->ani[0].ofdmPhyErrBase);
|
|
ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
|
|
ah->ani[0].cckPhyErrBase);
|
|
|
|
ENABLE_REGWRITE_BUFFER(ah);
|
|
|
|
REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
|
|
REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
|
|
|
|
REGWRITE_BUFFER_FLUSH(ah);
|
|
DISABLE_REGWRITE_BUFFER(ah);
|
|
|
|
ath9k_enable_mib_counters(ah);
|
|
|
|
ah->aniperiod = ATH9K_ANI_PERIOD;
|
|
if (ah->config.enable_ani)
|
|
ah->proc_phyerr |= HAL_PROCESS_ANI;
|
|
}
|