mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 09:25:19 +07:00
1cbbf69cc8
Fix hw queue configuration since mt76x2 devices use a reverse queue
enumeration respect to mac80211 one:
- 0: AC_BE
- 1: AC_BK
- 2: AC_VI
- 3: AC_VO
The issue can be reproduced sending two concurrent flow using
two separate queues:
- VO: 20Mbps UDP traffic
- BE: TCP traffic
In this scenario the UDP traffic will be blocked by the TCP one.
Fix it configuring properly WMM hw queue parameters
Fixes: 7bc04215a6
("mt76: add driver code for MT76x2e")
Tested-by: Gaetano Catalli <gaetano.catalli@gmail.com>
Signed-off-by: Gaetano Catalli <gaetano.catalli@gmail.com>
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com>
Acked-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
185 lines
4.5 KiB
C
185 lines
4.5 KiB
C
/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "mt76x2.h"
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#include "mt76x2_dma.h"
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int
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mt76x2_tx_queue_mcu(struct mt76x2_dev *dev, enum mt76_txq_id qid,
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struct sk_buff *skb, int cmd, int seq)
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{
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struct mt76_queue *q = &dev->mt76.q_tx[qid];
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struct mt76_queue_buf buf;
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dma_addr_t addr;
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u32 tx_info;
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tx_info = MT_MCU_MSG_TYPE_CMD |
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FIELD_PREP(MT_MCU_MSG_CMD_TYPE, cmd) |
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FIELD_PREP(MT_MCU_MSG_CMD_SEQ, seq) |
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FIELD_PREP(MT_MCU_MSG_PORT, CPU_TX_PORT) |
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FIELD_PREP(MT_MCU_MSG_LEN, skb->len);
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addr = dma_map_single(dev->mt76.dev, skb->data, skb->len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev->mt76.dev, addr))
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return -ENOMEM;
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buf.addr = addr;
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buf.len = skb->len;
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spin_lock_bh(&q->lock);
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mt76_queue_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
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mt76_queue_kick(dev, q);
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spin_unlock_bh(&q->lock);
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return 0;
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}
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static int
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mt76x2_init_tx_queue(struct mt76x2_dev *dev, struct mt76_queue *q,
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int idx, int n_desc)
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{
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int ret;
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q->regs = dev->mt76.regs + MT_TX_RING_BASE + idx * MT_RING_SIZE;
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q->ndesc = n_desc;
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q->hw_idx = idx;
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ret = mt76_queue_alloc(dev, q);
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if (ret)
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return ret;
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mt76x2_irq_enable(dev, MT_INT_TX_DONE(idx));
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return 0;
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}
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void mt76x2_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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struct sk_buff *skb)
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{
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struct mt76x2_dev *dev = container_of(mdev, struct mt76x2_dev, mt76);
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void *rxwi = skb->data;
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if (q == MT_RXQ_MCU) {
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skb_queue_tail(&dev->mcu.res_q, skb);
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wake_up(&dev->mcu.wait);
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return;
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}
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skb_pull(skb, sizeof(struct mt76x2_rxwi));
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if (mt76x2_mac_process_rx(dev, skb, rxwi)) {
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dev_kfree_skb(skb);
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return;
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}
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mt76_rx(&dev->mt76, q, skb);
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}
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static int
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mt76x2_init_rx_queue(struct mt76x2_dev *dev, struct mt76_queue *q,
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int idx, int n_desc, int bufsize)
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{
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int ret;
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q->regs = dev->mt76.regs + MT_RX_RING_BASE + idx * MT_RING_SIZE;
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q->ndesc = n_desc;
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q->buf_size = bufsize;
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ret = mt76_queue_alloc(dev, q);
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if (ret)
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return ret;
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mt76x2_irq_enable(dev, MT_INT_RX_DONE(idx));
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return 0;
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}
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static void
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mt76x2_tx_tasklet(unsigned long data)
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{
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struct mt76x2_dev *dev = (struct mt76x2_dev *) data;
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int i;
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mt76x2_mac_process_tx_status_fifo(dev);
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for (i = MT_TXQ_MCU; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76x2_mac_poll_tx_status(dev, false);
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mt76x2_irq_enable(dev, MT_INT_TX_DONE_ALL);
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}
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int mt76x2_dma_init(struct mt76x2_dev *dev)
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{
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static const u8 wmm_queue_map[] = {
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[IEEE80211_AC_BE] = 0,
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[IEEE80211_AC_BK] = 1,
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[IEEE80211_AC_VI] = 2,
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[IEEE80211_AC_VO] = 3,
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};
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int ret;
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int i;
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struct mt76_txwi_cache __maybe_unused *t;
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struct mt76_queue *q;
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BUILD_BUG_ON(sizeof(t->txwi) < sizeof(struct mt76x2_txwi));
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BUILD_BUG_ON(sizeof(struct mt76x2_rxwi) > MT_RX_HEADROOM);
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mt76_dma_attach(&dev->mt76);
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init_waitqueue_head(&dev->mcu.wait);
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skb_queue_head_init(&dev->mcu.res_q);
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tasklet_init(&dev->tx_tasklet, mt76x2_tx_tasklet, (unsigned long) dev);
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mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
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for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
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ret = mt76x2_init_tx_queue(dev, &dev->mt76.q_tx[i],
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wmm_queue_map[i], MT_TX_RING_SIZE);
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if (ret)
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return ret;
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}
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ret = mt76x2_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD],
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MT_TX_HW_QUEUE_MGMT, MT_TX_RING_SIZE);
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if (ret)
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return ret;
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ret = mt76x2_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
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MT_TX_HW_QUEUE_MCU, MT_MCU_RING_SIZE);
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if (ret)
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return ret;
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ret = mt76x2_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
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MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
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if (ret)
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return ret;
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q = &dev->mt76.q_rx[MT_RXQ_MAIN];
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q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x2_rxwi);
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ret = mt76x2_init_rx_queue(dev, q, 0, MT76x2_RX_RING_SIZE, MT_RX_BUF_SIZE);
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if (ret)
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return ret;
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return mt76_init_queues(dev);
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}
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void mt76x2_dma_cleanup(struct mt76x2_dev *dev)
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{
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tasklet_kill(&dev->tx_tasklet);
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mt76_dma_cleanup(&dev->mt76);
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}
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