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c83c8e6cde
In OMAP4, MMC1 PBIAS and its associated IO is software-controlled by CONTROL_PBIAS and CONTROL_MMC1 registers. This patch adds PBIAS configuration for MMC1 Controller during power-ON and power-OFF of regulator. Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
382 lines
17 KiB
C
382 lines
17 KiB
C
/*
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* arch/arm/plat-omap/include/mach/control.h
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*
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* OMAP2/3/4 System Control Module definitions
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*
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* Copyright (C) 2007-2009 Texas Instruments, Inc.
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* Copyright (C) 2007-2008 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_CONTROL_H
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#define __ASM_ARCH_CONTROL_H
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#include <mach/io.h>
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#ifndef __ASSEMBLY__
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#define OMAP242X_CTRL_REGADDR(reg) \
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OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
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#define OMAP243X_CTRL_REGADDR(reg) \
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OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
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#define OMAP343X_CTRL_REGADDR(reg) \
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OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
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#else
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#define OMAP242X_CTRL_REGADDR(reg) \
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OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
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#define OMAP243X_CTRL_REGADDR(reg) \
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OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
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#define OMAP343X_CTRL_REGADDR(reg) \
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OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
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#endif /* __ASSEMBLY__ */
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/*
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* As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
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* OMAP24XX and OMAP34XX.
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*/
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/* Control submodule offsets */
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#define OMAP2_CONTROL_INTERFACE 0x000
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#define OMAP2_CONTROL_PADCONFS 0x030
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#define OMAP2_CONTROL_GENERAL 0x270
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#define OMAP343X_CONTROL_MEM_WKUP 0x600
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#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
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#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
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/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
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#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
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/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
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#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
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#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
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#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
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#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
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#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
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#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
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#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
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#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
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#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
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#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
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#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
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#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
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/* 242x-only CONTROL_GENERAL register offsets */
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#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
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#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
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/* 243x-only CONTROL_GENERAL register offsets */
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/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
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#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
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#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
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#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
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#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
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#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
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#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
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/* 24xx-only CONTROL_GENERAL register offsets */
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#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
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#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
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#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
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#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
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#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
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#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
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#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
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#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
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#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
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#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
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#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
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#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
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#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
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#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
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#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
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#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
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#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
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#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
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#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
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#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
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#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
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#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
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#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
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#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
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#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
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#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
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#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
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#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
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#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
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#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
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#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
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#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
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/* 34xx-only CONTROL_GENERAL register offsets */
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#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
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#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
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#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
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#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
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#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
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#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
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#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
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#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
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#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
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#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
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#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
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#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
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#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
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#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
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#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
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#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
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#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
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#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
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#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
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#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
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#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
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#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
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#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
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#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
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#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
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#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
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#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
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#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
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#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
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#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
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#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
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#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
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+ ((i) >> 1) * 4 + (!((i) & 1)) * 2)
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#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
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#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
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#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
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#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
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#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
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#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
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#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
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#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
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#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
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#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
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#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
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/* AM35XX only CONTROL_GENERAL register offsets */
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#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
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#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
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#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314)
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#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320)
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#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324)
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#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328)
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#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C)
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/* 34xx PADCONF register offsets */
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#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
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(i)*2)
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#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
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#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
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#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
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#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
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#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
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#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
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#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
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#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
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#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
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#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
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#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
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#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
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#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
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#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
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#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
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#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
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#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
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#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
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/* 34xx GENERAL_WKUP regist offsets */
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#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
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0x008 + (i))
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#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
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#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
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#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
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#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
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#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
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/* 34xx D2D idle-related pins, handled by PM core */
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#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
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#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
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/* 44xx control status register offset */
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#define OMAP44XX_CONTROL_STATUS 0x2c4
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/* 44xx-only CONTROL_GENERAL register offsets */
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#define OMAP44XX_CONTROL_MMC1 0x628
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#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
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/*
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* REVISIT: This list of registers is not comprehensive - there are more
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* that should be added.
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*/
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/*
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* Control module register bit defines - these should eventually go into
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* their own regbits file. Some of these will be complicated, depending
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* on the device type (general-purpose, emulator, test, secure, bad, other)
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* and the security mode (secure, non-secure, don't care)
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*/
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/* CONTROL_DEVCONF0 bits */
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#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
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#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
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#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
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#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
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/* CONTROL_DEVCONF1 bits */
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#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
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#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
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#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
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#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
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#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
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/* CONTROL_STATUS bits */
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#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
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#define OMAP2_SYSBOOT_5_MASK (1 << 5)
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#define OMAP2_SYSBOOT_4_MASK (1 << 4)
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#define OMAP2_SYSBOOT_3_MASK (1 << 3)
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#define OMAP2_SYSBOOT_2_MASK (1 << 2)
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#define OMAP2_SYSBOOT_1_MASK (1 << 1)
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#define OMAP2_SYSBOOT_0_MASK (1 << 0)
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/* CONTROL_PBIAS_LITE bits */
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#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
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#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
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#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
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#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
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#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
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#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
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#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
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#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
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#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
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#define OMAP2_PBIASLITEVMODE0 (1 << 0)
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/* CONTROL_PBIAS_LITE bits for OMAP4 */
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#define OMAP4_MMC1_PWRDNZ (1 << 26)
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#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
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#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
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#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
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#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
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#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
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#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
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#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
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#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
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#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
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#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
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#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
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#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
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#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
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/* CONTROL_PROG_IO1 bits */
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#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
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/* CONTROL_IVA2_BOOTMOD bits */
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#define OMAP3_IVA2_BOOTMOD_SHIFT 0
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#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
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#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
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/* CONTROL_PADCONF_X bits */
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#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
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#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
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#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
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#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
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#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
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/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
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#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
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#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
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#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
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#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
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#define AM35XX_USBOTG_FCLK_SHIFT 8
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#define AM35XX_CPGMAC_FCLK_SHIFT 9
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#define AM35XX_VPFE_FCLK_SHIFT 10
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/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
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#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
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#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
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#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
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#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
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#define AM35XX_USBOTGSS_INT_CLR BIT(4)
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#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
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#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
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#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
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/*AM35XX CONTROL_IP_SW_RESET bits*/
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#define AM35XX_USBOTGSS_SW_RST BIT(0)
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#define AM35XX_CPGMACSS_SW_RST BIT(1)
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#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
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#define AM35XX_HECC_SW_RST BIT(3)
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#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
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/*
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* CONTROL OMAP STATUS register to identify OMAP3 features
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*/
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#define OMAP3_CONTROL_OMAP_STATUS 0x044c
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#define OMAP3_SGX_SHIFT 13
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#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
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#define FEAT_SGX_FULL 0
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#define FEAT_SGX_HALF 1
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#define FEAT_SGX_NONE 2
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#define OMAP3_IVA_SHIFT 12
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#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
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#define FEAT_IVA 0
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#define FEAT_IVA_NONE 1
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#define OMAP3_L2CACHE_SHIFT 10
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#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
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#define FEAT_L2CACHE_NONE 0
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#define FEAT_L2CACHE_64KB 1
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#define FEAT_L2CACHE_128KB 2
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#define FEAT_L2CACHE_256KB 3
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#define OMAP3_ISP_SHIFT 5
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#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
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#define FEAT_ISP 0
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#define FEAT_ISP_NONE 1
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#define OMAP3_NEON_SHIFT 4
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#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
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#define FEAT_NEON 0
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#define FEAT_NEON_NONE 1
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_ARCH_OMAP2PLUS
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extern void __iomem *omap_ctrl_base_get(void);
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extern u8 omap_ctrl_readb(u16 offset);
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extern u16 omap_ctrl_readw(u16 offset);
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extern u32 omap_ctrl_readl(u16 offset);
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extern void omap_ctrl_writeb(u8 val, u16 offset);
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extern void omap_ctrl_writew(u16 val, u16 offset);
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extern void omap_ctrl_writel(u32 val, u16 offset);
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extern void omap3_save_scratchpad_contents(void);
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extern void omap3_clear_scratchpad_contents(void);
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extern u32 *get_restore_pointer(void);
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extern u32 *get_es3_restore_pointer(void);
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extern u32 omap3_arm_context[128];
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extern void omap3_control_save_context(void);
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extern void omap3_control_restore_context(void);
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#else
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#define omap_ctrl_base_get() 0
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#define omap_ctrl_readb(x) 0
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#define omap_ctrl_readw(x) 0
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#define omap_ctrl_readl(x) 0
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#define omap_ctrl_writeb(x, y) WARN_ON(1)
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#define omap_ctrl_writew(x, y) WARN_ON(1)
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#define omap_ctrl_writel(x, y) WARN_ON(1)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_CONTROL_H */
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