mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 09:05:12 +07:00
ef092dec04
Keep the page at address 0 as faulting to catch any potential state setup issues early. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
337 lines
8.9 KiB
C
337 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Etnaviv Project
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*/
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitops.h>
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_gpu.h"
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#include "etnaviv_mmu.h"
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#include "etnaviv_iommu.h"
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#include "state.xml.h"
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#include "state_hi.xml.h"
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#define MMUv2_PTE_PRESENT BIT(0)
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#define MMUv2_PTE_EXCEPTION BIT(1)
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#define MMUv2_PTE_WRITEABLE BIT(2)
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#define MMUv2_MTLB_MASK 0xffc00000
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#define MMUv2_MTLB_SHIFT 22
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#define MMUv2_STLB_MASK 0x003ff000
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#define MMUv2_STLB_SHIFT 12
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#define MMUv2_MAX_STLB_ENTRIES 1024
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struct etnaviv_iommuv2_domain {
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struct etnaviv_iommu_domain base;
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/* P(age) T(able) A(rray) */
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u64 *pta_cpu;
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dma_addr_t pta_dma;
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/* M(aster) TLB aka first level pagetable */
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u32 *mtlb_cpu;
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dma_addr_t mtlb_dma;
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/* S(lave) TLB aka second level pagetable */
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u32 *stlb_cpu[MMUv2_MAX_STLB_ENTRIES];
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dma_addr_t stlb_dma[MMUv2_MAX_STLB_ENTRIES];
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};
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static struct etnaviv_iommuv2_domain *
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to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
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{
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return container_of(domain, struct etnaviv_iommuv2_domain, base);
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}
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static int
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etnaviv_iommuv2_ensure_stlb(struct etnaviv_iommuv2_domain *etnaviv_domain,
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int stlb)
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{
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if (etnaviv_domain->stlb_cpu[stlb])
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return 0;
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etnaviv_domain->stlb_cpu[stlb] =
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dma_alloc_wc(etnaviv_domain->base.dev, SZ_4K,
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&etnaviv_domain->stlb_dma[stlb],
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GFP_KERNEL);
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if (!etnaviv_domain->stlb_cpu[stlb])
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return -ENOMEM;
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memset32(etnaviv_domain->stlb_cpu[stlb], MMUv2_PTE_EXCEPTION,
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SZ_4K / sizeof(u32));
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etnaviv_domain->mtlb_cpu[stlb] = etnaviv_domain->stlb_dma[stlb] |
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MMUv2_PTE_PRESENT;
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return 0;
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}
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static int etnaviv_iommuv2_map(struct etnaviv_iommu_domain *domain,
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unsigned long iova, phys_addr_t paddr,
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size_t size, int prot)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int mtlb_entry, stlb_entry, ret;
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u32 entry = lower_32_bits(paddr) | MMUv2_PTE_PRESENT;
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if (size != SZ_4K)
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return -EINVAL;
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if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
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entry |= (upper_32_bits(paddr) & 0xff) << 4;
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if (prot & ETNAVIV_PROT_WRITE)
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entry |= MMUv2_PTE_WRITEABLE;
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mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
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stlb_entry = (iova & MMUv2_STLB_MASK) >> MMUv2_STLB_SHIFT;
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ret = etnaviv_iommuv2_ensure_stlb(etnaviv_domain, mtlb_entry);
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if (ret)
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return ret;
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etnaviv_domain->stlb_cpu[mtlb_entry][stlb_entry] = entry;
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return 0;
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}
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static size_t etnaviv_iommuv2_unmap(struct etnaviv_iommu_domain *domain,
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unsigned long iova, size_t size)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int mtlb_entry, stlb_entry;
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if (size != SZ_4K)
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return -EINVAL;
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mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
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stlb_entry = (iova & MMUv2_STLB_MASK) >> MMUv2_STLB_SHIFT;
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etnaviv_domain->stlb_cpu[mtlb_entry][stlb_entry] = MMUv2_PTE_EXCEPTION;
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return SZ_4K;
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}
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static int etnaviv_iommuv2_init(struct etnaviv_iommuv2_domain *etnaviv_domain)
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{
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int ret;
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/* allocate scratch page */
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etnaviv_domain->base.bad_page_cpu =
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dma_alloc_wc(etnaviv_domain->base.dev, SZ_4K,
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&etnaviv_domain->base.bad_page_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->base.bad_page_cpu) {
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ret = -ENOMEM;
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goto fail_mem;
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}
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memset32(etnaviv_domain->base.bad_page_cpu, 0xdead55aa,
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SZ_4K / sizeof(u32));
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etnaviv_domain->pta_cpu = dma_alloc_wc(etnaviv_domain->base.dev,
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SZ_4K, &etnaviv_domain->pta_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->pta_cpu) {
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ret = -ENOMEM;
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goto fail_mem;
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}
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etnaviv_domain->mtlb_cpu = dma_alloc_wc(etnaviv_domain->base.dev,
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SZ_4K, &etnaviv_domain->mtlb_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->mtlb_cpu) {
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ret = -ENOMEM;
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goto fail_mem;
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}
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memset32(etnaviv_domain->mtlb_cpu, MMUv2_PTE_EXCEPTION,
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MMUv2_MAX_STLB_ENTRIES);
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return 0;
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fail_mem:
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if (etnaviv_domain->base.bad_page_cpu)
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dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->base.bad_page_cpu,
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etnaviv_domain->base.bad_page_dma);
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if (etnaviv_domain->pta_cpu)
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dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->pta_cpu, etnaviv_domain->pta_dma);
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if (etnaviv_domain->mtlb_cpu)
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dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->mtlb_cpu, etnaviv_domain->mtlb_dma);
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return ret;
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}
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static void etnaviv_iommuv2_domain_free(struct etnaviv_iommu_domain *domain)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int i;
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dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->base.bad_page_cpu,
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etnaviv_domain->base.bad_page_dma);
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dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->pta_cpu, etnaviv_domain->pta_dma);
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dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->mtlb_cpu, etnaviv_domain->mtlb_dma);
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
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if (etnaviv_domain->stlb_cpu[i])
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dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->stlb_cpu[i],
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etnaviv_domain->stlb_dma[i]);
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}
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vfree(etnaviv_domain);
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}
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static size_t etnaviv_iommuv2_dump_size(struct etnaviv_iommu_domain *domain)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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size_t dump_size = SZ_4K;
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int i;
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++)
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if (etnaviv_domain->mtlb_cpu[i] & MMUv2_PTE_PRESENT)
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dump_size += SZ_4K;
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return dump_size;
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}
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static void etnaviv_iommuv2_dump(struct etnaviv_iommu_domain *domain, void *buf)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int i;
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memcpy(buf, etnaviv_domain->mtlb_cpu, SZ_4K);
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buf += SZ_4K;
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++, buf += SZ_4K)
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if (etnaviv_domain->mtlb_cpu[i] & MMUv2_PTE_PRESENT)
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memcpy(buf, etnaviv_domain->stlb_cpu[i], SZ_4K);
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}
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static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(gpu->mmu->domain);
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u16 prefetch;
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/* If the MMU is already enabled the state is still there. */
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if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE)
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return;
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prefetch = etnaviv_buffer_config_mmuv2(gpu,
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(u32)etnaviv_domain->mtlb_dma,
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(u32)etnaviv_domain->base.bad_page_dma);
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etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
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prefetch);
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etnaviv_gpu_wait_idle(gpu, 100);
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gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
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}
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static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(gpu->mmu->domain);
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u16 prefetch;
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/* If the MMU is already enabled the state is still there. */
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if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE)
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return;
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gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW,
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lower_32_bits(etnaviv_domain->pta_dma));
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gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH,
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upper_32_bits(etnaviv_domain->pta_dma));
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gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE);
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gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW,
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lower_32_bits(etnaviv_domain->base.bad_page_dma));
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gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW,
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lower_32_bits(etnaviv_domain->base.bad_page_dma));
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gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG,
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VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(
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upper_32_bits(etnaviv_domain->base.bad_page_dma)) |
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VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(
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upper_32_bits(etnaviv_domain->base.bad_page_dma)));
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etnaviv_domain->pta_cpu[0] = etnaviv_domain->mtlb_dma |
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VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K;
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/* trigger a PTA load through the FE */
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prefetch = etnaviv_buffer_config_pta(gpu);
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etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
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prefetch);
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etnaviv_gpu_wait_idle(gpu, 100);
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gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE);
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}
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void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
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{
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switch (gpu->sec_mode) {
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case ETNA_SEC_NONE:
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etnaviv_iommuv2_restore_nonsec(gpu);
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break;
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case ETNA_SEC_KERNEL:
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etnaviv_iommuv2_restore_sec(gpu);
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break;
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default:
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WARN(1, "unhandled GPU security mode\n");
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break;
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}
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}
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static const struct etnaviv_iommu_domain_ops etnaviv_iommuv2_ops = {
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.free = etnaviv_iommuv2_domain_free,
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.map = etnaviv_iommuv2_map,
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.unmap = etnaviv_iommuv2_unmap,
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.dump_size = etnaviv_iommuv2_dump_size,
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.dump = etnaviv_iommuv2_dump,
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};
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struct etnaviv_iommu_domain *
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etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain;
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struct etnaviv_iommu_domain *domain;
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int ret;
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etnaviv_domain = vzalloc(sizeof(*etnaviv_domain));
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if (!etnaviv_domain)
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return NULL;
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domain = &etnaviv_domain->base;
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domain->dev = gpu->dev;
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domain->base = SZ_4K;
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domain->size = (u64)SZ_1G * 4 - SZ_4K;
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domain->ops = &etnaviv_iommuv2_ops;
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ret = etnaviv_iommuv2_init(etnaviv_domain);
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if (ret)
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goto out_free;
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return &etnaviv_domain->base;
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out_free:
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vfree(etnaviv_domain);
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return NULL;
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}
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