mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 08:36:27 +07:00
ac3167257b
At over 4000 #includes, <linux/platform_device.h> is the 9th most
#included header file in the Linux kernel. It does not need
<linux/mod_devicetable.h>, so drop that header and explicitly add
<linux/mod_devicetable.h> to source files that need it.
4146 #include <linux/platform_device.h>
After this patch, there are 225 files that use <linux/mod_devicetable.h>,
for a reduction of around 3900 times that <linux/mod_devicetable.h>
does not have to be read & parsed.
225 #include <linux/mod_devicetable.h>
This patch was build-tested on 20 different arch-es.
It also makes these drivers SubmitChecklist#1 compliant.
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kbuild test robot <lkp@intel.com> # drivers/media/platform/vimc/
Reported-by: kbuild test robot <lkp@intel.com> # drivers/pinctrl/pinctrl-u300.c
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
194 lines
4.8 KiB
C
194 lines
4.8 KiB
C
/*
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* Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Luotao Fu, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/w1.h>
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/*
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* MXC W1 Register offsets
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*/
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#define MXC_W1_CONTROL 0x00
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# define MXC_W1_CONTROL_RDST BIT(3)
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# define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
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# define MXC_W1_CONTROL_PST BIT(6)
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# define MXC_W1_CONTROL_RPP BIT(7)
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#define MXC_W1_TIME_DIVIDER 0x02
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#define MXC_W1_RESET 0x04
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# define MXC_W1_RESET_RST BIT(0)
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struct mxc_w1_device {
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void __iomem *regs;
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struct clk *clk;
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struct w1_bus_master bus_master;
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};
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/*
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* this is the low level routine to
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* reset the device on the One Wire interface
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* on the hardware
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*/
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static u8 mxc_w1_ds2_reset_bus(void *data)
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{
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struct mxc_w1_device *dev = data;
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unsigned long timeout;
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writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
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/* Wait for reset sequence 511+512us, use 1500us for sure */
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timeout = jiffies + usecs_to_jiffies(1500);
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udelay(511 + 512);
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do {
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u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
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/* PST bit is valid after the RPP bit is self-cleared */
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if (!(ctrl & MXC_W1_CONTROL_RPP))
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return !(ctrl & MXC_W1_CONTROL_PST);
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} while (time_is_after_jiffies(timeout));
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return 1;
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}
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/*
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* this is the low level routine to read/write a bit on the One Wire
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* interface on the hardware. It does write 0 if parameter bit is set
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* to 0, otherwise a write 1/read.
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*/
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static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
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{
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struct mxc_w1_device *dev = data;
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unsigned long timeout;
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writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
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/* Wait for read/write bit (60us, Max 120us), use 200us for sure */
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timeout = jiffies + usecs_to_jiffies(200);
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udelay(60);
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do {
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u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
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/* RDST bit is valid after the WR1/RD bit is self-cleared */
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if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
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return !!(ctrl & MXC_W1_CONTROL_RDST);
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} while (time_is_after_jiffies(timeout));
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return 0;
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}
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static int mxc_w1_probe(struct platform_device *pdev)
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{
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struct mxc_w1_device *mdev;
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unsigned long clkrate;
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struct resource *res;
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unsigned int clkdiv;
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int err;
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mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
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GFP_KERNEL);
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if (!mdev)
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return -ENOMEM;
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mdev->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(mdev->clk))
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return PTR_ERR(mdev->clk);
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err = clk_prepare_enable(mdev->clk);
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if (err)
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return err;
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clkrate = clk_get_rate(mdev->clk);
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if (clkrate < 10000000)
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dev_warn(&pdev->dev,
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"Low clock frequency causes improper function\n");
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clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
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clkrate /= clkdiv;
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if ((clkrate < 980000) || (clkrate > 1020000))
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dev_warn(&pdev->dev,
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"Incorrect time base frequency %lu Hz\n", clkrate);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mdev->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mdev->regs)) {
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err = PTR_ERR(mdev->regs);
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goto out_disable_clk;
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}
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/* Software reset 1-Wire module */
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writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET);
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writeb(0, mdev->regs + MXC_W1_RESET);
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writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
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mdev->bus_master.data = mdev;
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mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
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mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
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platform_set_drvdata(pdev, mdev);
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err = w1_add_master_device(&mdev->bus_master);
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if (err)
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goto out_disable_clk;
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return 0;
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out_disable_clk:
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clk_disable_unprepare(mdev->clk);
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return err;
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}
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/*
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* disassociate the w1 device from the driver
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*/
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static int mxc_w1_remove(struct platform_device *pdev)
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{
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struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
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w1_remove_master_device(&mdev->bus_master);
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clk_disable_unprepare(mdev->clk);
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return 0;
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}
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static const struct of_device_id mxc_w1_dt_ids[] = {
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{ .compatible = "fsl,imx21-owire" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
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static struct platform_driver mxc_w1_driver = {
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.driver = {
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.name = "mxc_w1",
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.of_match_table = mxc_w1_dt_ids,
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},
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.probe = mxc_w1_probe,
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.remove = mxc_w1_remove,
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};
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module_platform_driver(mxc_w1_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Freescale Semiconductors Inc");
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MODULE_DESCRIPTION("Driver for One-Wire on MXC");
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