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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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53b3d9c3fd
Setting PA_PWRMode using DME_SET triggers the power mode change. And then the result will be given by the HCS.UPMCRS. This operation should be done atomically. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org> Tested-by: Yaniv Gardi <ygardi@codeaurora.org> Signed-off-by: Santosh Y <santoshsy@gmail.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
386 lines
11 KiB
C
386 lines
11 KiB
C
/*
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* Universal Flash Storage Host controller driver
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*
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* This code is based on drivers/scsi/ufs/ufshci.h
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* Copyright (C) 2011-2013 Samsung India Software Operations
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*
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* Authors:
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* Santosh Yaraganavi <santosh.sy@samsung.com>
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* Vinayak Holikatti <h.vinayak@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* See the COPYING file in the top-level directory or visit
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This program is provided "AS IS" and "WITH ALL FAULTS" and
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* without warranty of any kind. You are solely responsible for
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* determining the appropriateness of using and distributing
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* the program and assume all risks associated with your exercise
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* of rights with respect to the program, including but not limited
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* to infringement of third party rights, the risks and costs of
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* program errors, damage to or loss of data, programs or equipment,
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* and unavailability or interruption of operations. Under no
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* circumstances will the contributor of this Program be liable for
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* any damages of any kind arising from your use or distribution of
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* this program.
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*/
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#ifndef _UFSHCI_H
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#define _UFSHCI_H
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enum {
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TASK_REQ_UPIU_SIZE_DWORDS = 8,
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TASK_RSP_UPIU_SIZE_DWORDS = 8,
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ALIGNED_UPIU_SIZE = 512,
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};
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/* UFSHCI Registers */
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enum {
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REG_CONTROLLER_CAPABILITIES = 0x00,
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REG_UFS_VERSION = 0x08,
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REG_CONTROLLER_DEV_ID = 0x10,
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REG_CONTROLLER_PROD_ID = 0x14,
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REG_INTERRUPT_STATUS = 0x20,
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REG_INTERRUPT_ENABLE = 0x24,
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REG_CONTROLLER_STATUS = 0x30,
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REG_CONTROLLER_ENABLE = 0x34,
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REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
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REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
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REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
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REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
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REG_UIC_ERROR_CODE_DME = 0x48,
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REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
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REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
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REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
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REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
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REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
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REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
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REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
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REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
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REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
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REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
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REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
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REG_UIC_COMMAND = 0x90,
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REG_UIC_COMMAND_ARG_1 = 0x94,
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REG_UIC_COMMAND_ARG_2 = 0x98,
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REG_UIC_COMMAND_ARG_3 = 0x9C,
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};
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/* Controller capability masks */
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enum {
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MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
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MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
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MASK_64_ADDRESSING_SUPPORT = 0x01000000,
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MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
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MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
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};
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/* UFS Version 08h */
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#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
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#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
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/* Controller UFSHCI version */
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enum {
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UFSHCI_VERSION_10 = 0x00010000,
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UFSHCI_VERSION_11 = 0x00010100,
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};
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/*
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* HCDDID - Host Controller Identification Descriptor
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* - Device ID and Device Class 10h
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*/
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#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
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#define DEVICE_ID UFS_MASK(0xFF, 24)
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/*
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* HCPMID - Host Controller Identification Descriptor
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* - Product/Manufacturer ID 14h
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*/
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#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
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#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
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#define UFS_BIT(x) (1L << (x))
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#define UTP_TRANSFER_REQ_COMPL UFS_BIT(0)
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#define UIC_DME_END_PT_RESET UFS_BIT(1)
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#define UIC_ERROR UFS_BIT(2)
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#define UIC_TEST_MODE UFS_BIT(3)
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#define UIC_POWER_MODE UFS_BIT(4)
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#define UIC_HIBERNATE_EXIT UFS_BIT(5)
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#define UIC_HIBERNATE_ENTER UFS_BIT(6)
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#define UIC_LINK_LOST UFS_BIT(7)
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#define UIC_LINK_STARTUP UFS_BIT(8)
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#define UTP_TASK_REQ_COMPL UFS_BIT(9)
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#define UIC_COMMAND_COMPL UFS_BIT(10)
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#define DEVICE_FATAL_ERROR UFS_BIT(11)
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#define CONTROLLER_FATAL_ERROR UFS_BIT(16)
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#define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17)
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#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL |\
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UIC_POWER_MODE)
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#define UFSHCD_ERROR_MASK (UIC_ERROR |\
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DEVICE_FATAL_ERROR |\
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CONTROLLER_FATAL_ERROR |\
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SYSTEM_BUS_FATAL_ERROR)
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#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
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CONTROLLER_FATAL_ERROR |\
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SYSTEM_BUS_FATAL_ERROR)
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/* HCS - Host Controller Status 30h */
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#define DEVICE_PRESENT UFS_BIT(0)
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#define UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1)
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#define UTP_TASK_REQ_LIST_READY UFS_BIT(2)
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#define UIC_COMMAND_READY UFS_BIT(3)
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#define HOST_ERROR_INDICATOR UFS_BIT(4)
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#define DEVICE_ERROR_INDICATOR UFS_BIT(5)
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#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
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enum {
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PWR_OK = 0x0,
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PWR_LOCAL = 0x01,
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PWR_REMOTE = 0x02,
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PWR_BUSY = 0x03,
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PWR_ERROR_CAP = 0x04,
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PWR_FATAL_ERROR = 0x05,
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};
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/* HCE - Host Controller Enable 34h */
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#define CONTROLLER_ENABLE UFS_BIT(0)
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#define CONTROLLER_DISABLE 0x0
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/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
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#define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31)
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#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
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/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
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#define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31)
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#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
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#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
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/* UECN - Host UIC Error Code Network Layer 40h */
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#define UIC_NETWORK_LAYER_ERROR UFS_BIT(31)
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#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
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/* UECT - Host UIC Error Code Transport Layer 44h */
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#define UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31)
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#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
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/* UECDME - Host UIC Error Code DME 48h */
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#define UIC_DME_ERROR UFS_BIT(31)
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#define UIC_DME_ERROR_CODE_MASK 0x1
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#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
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#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
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#define INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16)
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#define INT_AGGR_STATUS_BIT UFS_BIT(20)
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#define INT_AGGR_PARAM_WRITE UFS_BIT(24)
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#define INT_AGGR_ENABLE UFS_BIT(31)
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/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
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#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
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/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
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#define UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
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/* UICCMD - UIC Command */
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#define COMMAND_OPCODE_MASK 0xFF
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#define GEN_SELECTOR_INDEX_MASK 0xFFFF
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#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
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#define RESET_LEVEL 0xFF
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#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
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#define CONFIG_RESULT_CODE_MASK 0xFF
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#define GENERIC_ERROR_CODE_MASK 0xFF
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#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
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((sel) & 0xFFFF))
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#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
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#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
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#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
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/* UIC Commands */
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enum {
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UIC_CMD_DME_GET = 0x01,
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UIC_CMD_DME_SET = 0x02,
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UIC_CMD_DME_PEER_GET = 0x03,
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UIC_CMD_DME_PEER_SET = 0x04,
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UIC_CMD_DME_POWERON = 0x10,
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UIC_CMD_DME_POWEROFF = 0x11,
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UIC_CMD_DME_ENABLE = 0x12,
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UIC_CMD_DME_RESET = 0x14,
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UIC_CMD_DME_END_PT_RST = 0x15,
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UIC_CMD_DME_LINK_STARTUP = 0x16,
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UIC_CMD_DME_HIBER_ENTER = 0x17,
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UIC_CMD_DME_HIBER_EXIT = 0x18,
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UIC_CMD_DME_TEST_MODE = 0x1A,
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};
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/* UIC Config result code / Generic error code */
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enum {
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UIC_CMD_RESULT_SUCCESS = 0x00,
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UIC_CMD_RESULT_INVALID_ATTR = 0x01,
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UIC_CMD_RESULT_FAILURE = 0x01,
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UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
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UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
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UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
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UIC_CMD_RESULT_BAD_INDEX = 0x05,
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UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
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UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
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UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
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UIC_CMD_RESULT_BUSY = 0x09,
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UIC_CMD_RESULT_DME_FAILURE = 0x0A,
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};
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#define MASK_UIC_COMMAND_RESULT 0xFF
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#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
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#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
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/* Interrupt disable masks */
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enum {
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/* Interrupt disable mask for UFSHCI v1.0 */
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INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
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INTERRUPT_MASK_RW_VER_10 = 0x30000,
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/* Interrupt disable mask for UFSHCI v1.1 */
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INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
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};
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/*
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* Request Descriptor Definitions
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*/
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/* Transfer request command type */
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enum {
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UTP_CMD_TYPE_SCSI = 0x0,
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UTP_CMD_TYPE_UFS = 0x1,
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UTP_CMD_TYPE_DEV_MANAGE = 0x2,
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};
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enum {
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UTP_SCSI_COMMAND = 0x00000000,
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UTP_NATIVE_UFS_COMMAND = 0x10000000,
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UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
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UTP_REQ_DESC_INT_CMD = 0x01000000,
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};
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/* UTP Transfer Request Data Direction (DD) */
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enum {
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UTP_NO_DATA_TRANSFER = 0x00000000,
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UTP_HOST_TO_DEVICE = 0x02000000,
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UTP_DEVICE_TO_HOST = 0x04000000,
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};
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/* Overall command status values */
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enum {
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OCS_SUCCESS = 0x0,
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OCS_INVALID_CMD_TABLE_ATTR = 0x1,
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OCS_INVALID_PRDT_ATTR = 0x2,
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OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
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OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
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OCS_PEER_COMM_FAILURE = 0x5,
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OCS_ABORTED = 0x6,
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OCS_FATAL_ERROR = 0x7,
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OCS_INVALID_COMMAND_STATUS = 0x0F,
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MASK_OCS = 0x0F,
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};
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/**
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* struct ufshcd_sg_entry - UFSHCI PRD Entry
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* @base_addr: Lower 32bit physical address DW-0
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* @upper_addr: Upper 32bit physical address DW-1
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* @reserved: Reserved for future use DW-2
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* @size: size of physical segment DW-3
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*/
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struct ufshcd_sg_entry {
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u32 base_addr;
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u32 upper_addr;
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u32 reserved;
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u32 size;
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};
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/**
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* struct utp_transfer_cmd_desc - UFS Command Descriptor structure
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* @command_upiu: Command UPIU Frame address
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* @response_upiu: Response UPIU Frame address
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* @prd_table: Physical Region Descriptor
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*/
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struct utp_transfer_cmd_desc {
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u8 command_upiu[ALIGNED_UPIU_SIZE];
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u8 response_upiu[ALIGNED_UPIU_SIZE];
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struct ufshcd_sg_entry prd_table[SG_ALL];
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};
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/**
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* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
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* @dword0: Descriptor Header DW0
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* @dword1: Descriptor Header DW1
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* @dword2: Descriptor Header DW2
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* @dword3: Descriptor Header DW3
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*/
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struct request_desc_header {
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u32 dword_0;
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u32 dword_1;
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u32 dword_2;
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u32 dword_3;
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};
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/**
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* struct utp_transfer_req_desc - UTRD structure
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* @header: UTRD header DW-0 to DW-3
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* @command_desc_base_addr_lo: UCD base address low DW-4
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* @command_desc_base_addr_hi: UCD base address high DW-5
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* @response_upiu_length: response UPIU length DW-6
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* @response_upiu_offset: response UPIU offset DW-6
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* @prd_table_length: Physical region descriptor length DW-7
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* @prd_table_offset: Physical region descriptor offset DW-7
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*/
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struct utp_transfer_req_desc {
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/* DW 0-3 */
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struct request_desc_header header;
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/* DW 4-5*/
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u32 command_desc_base_addr_lo;
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u32 command_desc_base_addr_hi;
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/* DW 6 */
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u16 response_upiu_length;
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u16 response_upiu_offset;
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/* DW 7 */
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u16 prd_table_length;
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u16 prd_table_offset;
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};
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/**
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* struct utp_task_req_desc - UTMRD structure
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* @header: UTMRD header DW-0 to DW-3
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* @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
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* @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
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*/
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struct utp_task_req_desc {
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/* DW 0-3 */
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struct request_desc_header header;
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/* DW 4-11 */
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u32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS];
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/* DW 12-19 */
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u32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS];
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};
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#endif /* End of Header */
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