mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 05:40:55 +07:00
376349232a
ARC AXS10x boards support custom IP-block which allows to control reset signals of selected peripherals. For example DW GMAC, etc... This block is controlled via memory-mapped register (AKA CREG) which represents up-to 32 reset lines. This regiter is self-clearing so we don't need to deassert line after reset. As of today only the following lines are used: - DW GMAC - line 5 Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
25 lines
960 B
Makefile
25 lines
960 B
Makefile
obj-y += core.o
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obj-y += hisilicon/
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obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
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obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
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obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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obj-$(CONFIG_RESET_HSDK_V1) += reset-hsdk-v1.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
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obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
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obj-$(CONFIG_RESET_MESON) += reset-meson.o
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obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
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obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_STM32) += reset-stm32.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
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obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o
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obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
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