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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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26efecf955
This patch adds a new API to clean up the scheduler job resources. This is primarliy needed in cases the job was created but was not queued to the scheduler queue. Additionally with this change, the layer which creates the scheduler job also gets to free up the job's resources and this entails moving the dma_fence_put(finished_fence) to the drivers ops free handler routines. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
247 lines
6.6 KiB
C
247 lines
6.6 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#include <linux/kthread.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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static void amdgpu_job_timedout(struct drm_sched_job *s_job)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
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struct amdgpu_job *job = to_amdgpu_job(s_job);
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if (amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
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DRM_ERROR("ring %s timeout, but soft recovered\n",
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s_job->sched->name);
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return;
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}
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DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
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job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
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ring->fence_drv.sync_seq);
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if (amdgpu_device_should_recover_gpu(ring->adev))
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amdgpu_device_gpu_recover(ring->adev, job);
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}
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int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
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struct amdgpu_job **job, struct amdgpu_vm *vm)
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{
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size_t size = sizeof(struct amdgpu_job);
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if (num_ibs == 0)
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return -EINVAL;
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size += sizeof(struct amdgpu_ib) * num_ibs;
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*job = kzalloc(size, GFP_KERNEL);
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if (!*job)
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return -ENOMEM;
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/*
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* Initialize the scheduler to at least some ring so that we always
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* have a pointer to adev.
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*/
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(*job)->base.sched = &adev->rings[0]->sched;
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(*job)->vm = vm;
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(*job)->ibs = (void *)&(*job)[1];
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(*job)->num_ibs = num_ibs;
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amdgpu_sync_create(&(*job)->sync);
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amdgpu_sync_create(&(*job)->sched_sync);
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(*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
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(*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
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return 0;
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}
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int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
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struct amdgpu_job **job)
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{
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int r;
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r = amdgpu_job_alloc(adev, 1, job, NULL);
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if (r)
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return r;
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r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
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if (r)
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kfree(*job);
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return r;
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}
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void amdgpu_job_free_resources(struct amdgpu_job *job)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
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struct dma_fence *f;
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unsigned i;
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/* use sched fence if available */
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f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
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for (i = 0; i < job->num_ibs; ++i)
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amdgpu_ib_free(ring->adev, &job->ibs[i], f);
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}
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static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
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struct amdgpu_job *job = to_amdgpu_job(s_job);
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drm_sched_job_cleanup(s_job);
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amdgpu_ring_priority_put(ring, s_job->s_priority);
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dma_fence_put(job->fence);
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amdgpu_sync_free(&job->sync);
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amdgpu_sync_free(&job->sched_sync);
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kfree(job);
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}
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void amdgpu_job_free(struct amdgpu_job *job)
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{
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amdgpu_job_free_resources(job);
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dma_fence_put(job->fence);
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amdgpu_sync_free(&job->sync);
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amdgpu_sync_free(&job->sched_sync);
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kfree(job);
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}
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int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
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void *owner, struct dma_fence **f)
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{
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enum drm_sched_priority priority;
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struct amdgpu_ring *ring;
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int r;
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if (!f)
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return -EINVAL;
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r = drm_sched_job_init(&job->base, entity, owner);
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if (r)
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return r;
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job->owner = owner;
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*f = dma_fence_get(&job->base.s_fence->finished);
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amdgpu_job_free_resources(job);
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priority = job->base.s_priority;
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drm_sched_entity_push_job(&job->base, entity);
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ring = to_amdgpu_ring(entity->rq->sched);
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amdgpu_ring_priority_get(ring, priority);
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return 0;
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}
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int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
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struct dma_fence **fence)
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{
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int r;
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job->base.sched = &ring->sched;
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r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence);
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job->fence = dma_fence_get(*fence);
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if (r)
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return r;
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amdgpu_job_free(job);
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return 0;
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}
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static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
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struct drm_sched_entity *s_entity)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
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struct amdgpu_job *job = to_amdgpu_job(sched_job);
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struct amdgpu_vm *vm = job->vm;
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struct dma_fence *fence;
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bool explicit = false;
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int r;
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fence = amdgpu_sync_get_fence(&job->sync, &explicit);
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if (fence && explicit) {
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if (drm_sched_dependency_optimized(fence, s_entity)) {
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r = amdgpu_sync_fence(ring->adev, &job->sched_sync,
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fence, false);
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if (r)
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DRM_ERROR("Error adding fence (%d)\n", r);
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}
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}
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while (fence == NULL && vm && !job->vmid) {
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r = amdgpu_vmid_grab(vm, ring, &job->sync,
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&job->base.s_fence->finished,
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job);
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if (r)
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DRM_ERROR("Error getting VM ID (%d)\n", r);
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fence = amdgpu_sync_get_fence(&job->sync, NULL);
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}
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return fence;
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}
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static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
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struct dma_fence *fence = NULL, *finished;
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struct amdgpu_job *job;
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int r;
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job = to_amdgpu_job(sched_job);
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finished = &job->base.s_fence->finished;
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BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
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trace_amdgpu_sched_run_job(job);
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if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter))
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dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
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if (finished->error < 0) {
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DRM_INFO("Skip scheduling IBs!\n");
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} else {
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r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
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&fence);
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if (r)
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DRM_ERROR("Error scheduling IBs (%d)\n", r);
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}
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/* if gpu reset, hw fence will be replaced here */
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dma_fence_put(job->fence);
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job->fence = dma_fence_get(fence);
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amdgpu_job_free_resources(job);
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return fence;
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}
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const struct drm_sched_backend_ops amdgpu_sched_ops = {
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.dependency = amdgpu_job_dependency,
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.run_job = amdgpu_job_run,
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.timedout_job = amdgpu_job_timedout,
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.free_job = amdgpu_job_free_cb
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};
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