mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
#ifndef __ASM_SH_CPU_SH5_CACHE_H
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#define __ASM_SH_CPU_SH5_CACHE_H
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/*
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* include/asm-sh/cpu-sh5/cache.h
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003, 2004 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define L1_CACHE_SHIFT 5
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/* Valid and Dirty bits */
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#define SH_CACHE_VALID (1LL<<0)
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#define SH_CACHE_UPDATED (1LL<<57)
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/* Unimplemented compat bits.. */
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#define SH_CACHE_COMBINED 0
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#define SH_CACHE_ASSOC 0
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/* Cache flags */
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#define SH_CACHE_MODE_WT (1LL<<0)
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#define SH_CACHE_MODE_WB (1LL<<1)
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/*
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* Control Registers.
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*/
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#define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */
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#define ICCR_REG0 0 /* Register 0 offset */
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#define ICCR_REG1 1 /* Register 1 offset */
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#define ICCR0 ICCR_BASE+ICCR_REG0
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#define ICCR1 ICCR_BASE+ICCR_REG1
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#define ICCR0_OFF 0x0 /* Set ICACHE off */
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#define ICCR0_ON 0x1 /* Set ICACHE on */
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#define ICCR0_ICI 0x2 /* Invalidate all in IC */
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#define ICCR1_NOLOCK 0x0 /* Set No Locking */
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#define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */
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#define OCCR_REG0 0 /* Register 0 offset */
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#define OCCR_REG1 1 /* Register 1 offset */
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#define OCCR0 OCCR_BASE+OCCR_REG0
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#define OCCR1 OCCR_BASE+OCCR_REG1
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#define OCCR0_OFF 0x0 /* Set OCACHE off */
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#define OCCR0_ON 0x1 /* Set OCACHE on */
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#define OCCR0_OCI 0x2 /* Invalidate all in OC */
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#define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
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#define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
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#define OCCR1_NOLOCK 0x0 /* Set No Locking */
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/*
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* SH-5
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* A bit of description here, for neff=32.
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*
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* |<--- tag (19 bits) --->|
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* +-----------------------------+-----------------+------+----------+------+
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* | | | ways |set index |offset|
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* +-----------------------------+-----------------+------+----------+------+
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* ^ 2 bits 8 bits 5 bits
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* +- Bit 31
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*
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* Cacheline size is based on offset: 5 bits = 32 bytes per line
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* A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
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* have a broader space for registers. These are outlined by
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* CACHE_?C_*_STEP below.
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*
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*/
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/* Instruction cache */
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#define CACHE_IC_ADDRESS_ARRAY 0x01000000
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/* Operand Cache */
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#define CACHE_OC_ADDRESS_ARRAY 0x01800000
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/* These declarations relate to cache 'synonyms' in the operand cache. A
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'synonym' occurs where effective address bits overlap between those used for
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indexing the cache sets and those passed to the MMU for translation. In the
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case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
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#define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
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#define CACHE_OC_SYN_SHIFT 12
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/* Mask to select synonym bit(s) */
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#define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
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/*
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* Instruction cache can't be invalidated based on physical addresses.
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* No Instruction Cache defines required, then.
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*/
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#endif /* __ASM_SH_CPU_SH5_CACHE_H */
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