mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 17:56:40 +07:00
2bc46b3ad3
Stop using alloc_ctx and just fill in the device pointer. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Cc: Federico Vaga <federico.vaga@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
196 lines
5.6 KiB
C
196 lines
5.6 KiB
C
/***************************************************************************
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* Copyright (C) 2006-2010 by Marin Mitov *
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* mitov@issp.bas.bg *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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***************************************************************************/
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/* DT3155 header file */
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#ifndef _DT3155_H_
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#define _DT3155_H_
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-dev.h>
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#include <media/videobuf2-v4l2.h>
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#define DT3155_NAME "dt3155"
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#define DT3155_VER_MAJ 2
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#define DT3155_VER_MIN 0
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#define DT3155_VER_EXT 0
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#define DT3155_VERSION __stringify(DT3155_VER_MAJ) "." \
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__stringify(DT3155_VER_MIN) "." \
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__stringify(DT3155_VER_EXT)
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/* DT3155 Base Register offsets (memory mapped) */
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#define EVEN_DMA_START 0x00
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#define ODD_DMA_START 0x0C
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#define EVEN_DMA_STRIDE 0x18
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#define ODD_DMA_STRIDE 0x24
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#define EVEN_PIXEL_FMT 0x30
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#define ODD_PIXEL_FMT 0x34
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#define FIFO_TRIGER 0x38
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#define XFER_MODE 0x3C
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#define CSR1 0x40
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#define RETRY_WAIT_CNT 0x44
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#define INT_CSR 0x48
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#define EVEN_FLD_MASK 0x4C
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#define ODD_FLD_MASK 0x50
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#define MASK_LENGTH 0x54
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#define FIFO_FLAG_CNT 0x58
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#define IIC_CLK_DUR 0x5C
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#define IIC_CSR1 0x60
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#define IIC_CSR2 0x64
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/* DT3155 Internal Registers indexes (i2c/IIC mapped) */
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#define CSR2 0x10
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#define EVEN_CSR 0x11
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#define ODD_CSR 0x12
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#define CONFIG 0x13
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#define DT_ID 0x1F
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#define X_CLIP_START 0x20
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#define Y_CLIP_START 0x22
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#define X_CLIP_END 0x24
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#define Y_CLIP_END 0x26
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#define AD_ADDR 0x30
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#define AD_LUT 0x31
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#define AD_CMD 0x32
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#define DIG_OUT 0x40
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#define PM_LUT_ADDR 0x50
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#define PM_LUT_DATA 0x51
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/* AD command register values */
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#define AD_CMD_REG 0x00
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#define AD_POS_REF 0x01
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#define AD_NEG_REF 0x02
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/* CSR1 bit masks */
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#define RANGE_EN 0x00008000
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#define CRPT_DIS 0x00004000
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#define ADDR_ERR_ODD 0x00000800
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#define ADDR_ERR_EVEN 0x00000400
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#define FLD_CRPT_ODD 0x00000200
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#define FLD_CRPT_EVEN 0x00000100
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#define FIFO_EN 0x00000080
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#define SRST 0x00000040
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#define FLD_DN_ODD 0x00000020
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#define FLD_DN_EVEN 0x00000010
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/* These should not be used.
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* Use CAP_CONT_ODD/EVEN instead
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#define CAP_SNGL_ODD 0x00000008
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#define CAP_SNGL_EVEN 0x00000004
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*/
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#define CAP_CONT_ODD 0x00000002
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#define CAP_CONT_EVEN 0x00000001
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/* INT_CSR bit masks */
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#define FLD_START_EN 0x00000400
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#define FLD_END_ODD_EN 0x00000200
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#define FLD_END_EVEN_EN 0x00000100
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#define FLD_START 0x00000004
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#define FLD_END_ODD 0x00000002
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#define FLD_END_EVEN 0x00000001
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/* IIC_CSR1 bit masks */
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#define DIRECT_ABORT 0x00000200
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/* IIC_CSR2 bit masks */
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#define NEW_CYCLE 0x01000000
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#define DIR_RD 0x00010000
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#define IIC_READ 0x01010000
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#define IIC_WRITE 0x01000000
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/* CSR2 bit masks */
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#define DISP_PASS 0x40
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#define BUSY_ODD 0x20
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#define BUSY_EVEN 0x10
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#define SYNC_PRESENT 0x08
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#define VT_50HZ 0x04
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#define SYNC_SNTL 0x02
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#define CHROM_FILT 0x01
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#define VT_60HZ 0x00
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/* CSR_EVEN/ODD bit masks */
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#define CSR_ERROR 0x04
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#define CSR_SNGL 0x02
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#define CSR_DONE 0x01
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/* CONFIG bit masks */
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#define PM_LUT_PGM 0x80
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#define PM_LUT_SEL 0x40
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#define CLIP_EN 0x20
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#define HSCALE_EN 0x10
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#define EXT_TRIG_UP 0x0C
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#define EXT_TRIG_DOWN 0x04
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#define ACQ_MODE_NEXT 0x02
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#define ACQ_MODE_ODD 0x01
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#define ACQ_MODE_EVEN 0x00
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/* AD_CMD bit masks */
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#define VIDEO_CNL_1 0x00
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#define VIDEO_CNL_2 0x40
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#define VIDEO_CNL_3 0x80
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#define VIDEO_CNL_4 0xC0
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#define SYNC_CNL_1 0x00
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#define SYNC_CNL_2 0x10
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#define SYNC_CNL_3 0x20
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#define SYNC_CNL_4 0x30
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#define SYNC_LVL_1 0x00
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#define SYNC_LVL_2 0x04
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#define SYNC_LVL_3 0x08
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#define SYNC_LVL_4 0x0C
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/* DT3155 identificator */
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#define DT3155_ID 0x20
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/* per board private data structure */
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/**
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* struct dt3155_priv - private data structure
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*
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* @v4l2_dev: v4l2_device structure
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* @vdev: video_device structure
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* @pdev: pointer to pci_dev structure
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* @vidq: vb2_queue structure
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* @curr_buf: pointer to curren buffer
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* @mux: mutex to protect the instance
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* @dmaq: queue for dma buffers
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* @lock: spinlock for dma queue
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* @std: input standard
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* @width: frame width
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* @height: frame height
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* @input: current input
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* @sequence: frame counter
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* @stats: statistics structure
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* @regs: local copy of mmio base register
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* @csr2: local copy of csr2 register
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* @config: local copy of config register
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*/
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struct dt3155_priv {
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struct v4l2_device v4l2_dev;
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struct video_device vdev;
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struct pci_dev *pdev;
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struct vb2_queue vidq;
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struct vb2_v4l2_buffer *curr_buf;
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struct mutex mux;
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struct list_head dmaq;
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spinlock_t lock;
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v4l2_std_id std;
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unsigned width, height;
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unsigned input;
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unsigned int sequence;
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void __iomem *regs;
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u8 csr2, config;
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};
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#endif /* _DT3155_H_ */
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