mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 14:26:42 +07:00
36954dc78d
We're assigning PE numbers after the completion of PCI probe. During the PCI probe, we had PE#0 as the super container to encompass all PCI devices. However, that's inappropriate since PELTM has ascending order of priority on search on P7IOC. So we need PE#127 takes the role that PE#0 has previously. For PHB3, we still have PE#0 as the reserved PE. The patch supposes that the underly firmware has built the RID to PE# mapping after resetting IODA tables: all PELTM entries except last one has invalid mapping on P7IOC, but all RTEs have binding to PE#0. The reserved PE# is being exported by firmware by device tree. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
||
|---|---|---|
| .. | ||
| eeh-ioda.c | ||
| eeh-powernv.c | ||
| Kconfig | ||
| Makefile | ||
| opal-flash.c | ||
| opal-lpc.c | ||
| opal-nvram.c | ||
| opal-rtc.c | ||
| opal-takeover.S | ||
| opal-wrappers.S | ||
| opal-xscom.c | ||
| opal.c | ||
| pci-ioda.c | ||
| pci-p5ioc2.c | ||
| pci.c | ||
| pci.h | ||
| powernv.h | ||
| rng.c | ||
| setup.c | ||
| smp.c | ||