mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 02:25:44 +07:00
36953aa94a
The vbios firmware structure changed between v3_1 and v3_2. So, the code to setup bootup values needs different paths based on header version. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
241 lines
7.3 KiB
C
241 lines
7.3 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef PP_ATOMFWCTRL_H
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#define PP_ATOMFWCTRL_H
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#include "hwmgr.h"
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typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
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#define GetIndexIntoMasterCmdTable(FieldName) \
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(((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
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#define GetIndexIntoMasterDataTable(FieldName) \
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(((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
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#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
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struct pp_atomfwctrl_voltage_table_entry {
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uint16_t value;
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uint32_t smio_low;
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};
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struct pp_atomfwctrl_voltage_table {
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uint32_t count;
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uint32_t mask_low;
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uint32_t phase_delay;
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uint8_t psi0_enable;
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uint8_t psi1_enable;
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uint8_t max_vid_step;
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uint8_t telemetry_offset;
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uint8_t telemetry_slope;
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struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
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};
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struct pp_atomfwctrl_gpio_pin_assignment {
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uint16_t us_gpio_pin_aindex;
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uint8_t uc_gpio_pin_bit_shift;
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};
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struct pp_atomfwctrl_clock_dividers_soc15 {
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uint32_t ulClock; /* the actual clock */
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uint32_t ulDid; /* DFS divider */
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uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
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uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
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uint16_t usPll_ss_slew_frac;
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uint8_t ucPll_ss_enable;
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uint8_t ucReserve;
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uint32_t ulReserve[2];
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};
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struct pp_atomfwctrl_avfs_parameters {
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uint32_t ulMaxVddc;
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uint32_t ulMinVddc;
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uint32_t ulMeanNsigmaAcontant0;
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uint32_t ulMeanNsigmaAcontant1;
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uint32_t ulMeanNsigmaAcontant2;
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uint16_t usMeanNsigmaDcTolSigma;
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uint16_t usMeanNsigmaPlatformMean;
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uint16_t usMeanNsigmaPlatformSigma;
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uint32_t ulGbVdroopTableCksoffA0;
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uint32_t ulGbVdroopTableCksoffA1;
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uint32_t ulGbVdroopTableCksoffA2;
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uint32_t ulGbVdroopTableCksonA0;
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uint32_t ulGbVdroopTableCksonA1;
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uint32_t ulGbVdroopTableCksonA2;
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uint32_t ulGbFuseTableCksoffM1;
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uint32_t ulGbFuseTableCksoffM2;
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uint32_t ulGbFuseTableCksoffB;
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uint32_t ulGbFuseTableCksonM1;
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uint32_t ulGbFuseTableCksonM2;
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uint32_t ulGbFuseTableCksonB;
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uint8_t ucEnableGbVdroopTableCkson;
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uint8_t ucEnableGbFuseTableCkson;
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uint16_t usPsmAgeComfactor;
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uint32_t ulDispclk2GfxclkM1;
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uint32_t ulDispclk2GfxclkM2;
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uint32_t ulDispclk2GfxclkB;
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uint32_t ulDcefclk2GfxclkM1;
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uint32_t ulDcefclk2GfxclkM2;
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uint32_t ulDcefclk2GfxclkB;
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uint32_t ulPixelclk2GfxclkM1;
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uint32_t ulPixelclk2GfxclkM2;
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uint32_t ulPixelclk2GfxclkB;
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uint32_t ulPhyclk2GfxclkM1;
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uint32_t ulPhyclk2GfxclkM2;
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uint32_t ulPhyclk2GfxclkB;
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uint32_t ulAcgGbVdroopTableA0;
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uint32_t ulAcgGbVdroopTableA1;
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uint32_t ulAcgGbVdroopTableA2;
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uint32_t ulAcgGbFuseTableM1;
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uint32_t ulAcgGbFuseTableM2;
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uint32_t ulAcgGbFuseTableB;
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uint32_t ucAcgEnableGbVdroopTable;
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uint32_t ucAcgEnableGbFuseTable;
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};
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struct pp_atomfwctrl_gpio_parameters {
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uint8_t ucAcDcGpio;
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uint8_t ucAcDcPolarity;
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uint8_t ucVR0HotGpio;
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uint8_t ucVR0HotPolarity;
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uint8_t ucVR1HotGpio;
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uint8_t ucVR1HotPolarity;
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uint8_t ucFwCtfGpio;
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uint8_t ucFwCtfPolarity;
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};
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struct pp_atomfwctrl_bios_boot_up_values {
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uint32_t ulRevision;
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uint32_t ulGfxClk;
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uint32_t ulUClk;
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uint32_t ulSocClk;
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uint32_t ulDCEFClk;
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uint32_t ulEClk;
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uint32_t ulVClk;
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uint32_t ulDClk;
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uint16_t usVddc;
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uint16_t usVddci;
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uint16_t usMvddc;
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uint16_t usVddGfx;
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uint8_t ucCoolingID;
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};
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struct pp_atomfwctrl_smc_dpm_parameters
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{
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uint8_t liquid1_i2c_address;
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uint8_t liquid2_i2c_address;
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uint8_t vr_i2c_address;
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uint8_t plx_i2c_address;
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uint8_t liquid_i2c_linescl;
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uint8_t liquid_i2c_linesda;
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uint8_t vr_i2c_linescl;
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uint8_t vr_i2c_linesda;
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uint8_t plx_i2c_linescl;
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uint8_t plx_i2c_linesda;
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uint8_t vrsensorpresent;
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uint8_t liquidsensorpresent;
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uint16_t maxvoltagestepgfx;
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uint16_t maxvoltagestepsoc;
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uint8_t vddgfxvrmapping;
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uint8_t vddsocvrmapping;
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uint8_t vddmem0vrmapping;
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uint8_t vddmem1vrmapping;
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uint8_t gfxulvphasesheddingmask;
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uint8_t soculvphasesheddingmask;
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uint16_t gfxmaxcurrent;
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uint8_t gfxoffset;
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uint8_t padding_telemetrygfx;
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uint16_t socmaxcurrent;
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uint8_t socoffset;
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uint8_t padding_telemetrysoc;
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uint16_t mem0maxcurrent;
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uint8_t mem0offset;
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uint8_t padding_telemetrymem0;
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uint16_t mem1maxcurrent;
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uint8_t mem1offset;
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uint8_t padding_telemetrymem1;
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uint8_t acdcgpio;
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uint8_t acdcpolarity;
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uint8_t vr0hotgpio;
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uint8_t vr0hotpolarity;
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uint8_t vr1hotgpio;
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uint8_t vr1hotpolarity;
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uint8_t padding1;
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uint8_t padding2;
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uint8_t ledpin0;
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uint8_t ledpin1;
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uint8_t ledpin2;
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uint8_t pllgfxclkspreadenabled;
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uint8_t pllgfxclkspreadpercent;
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uint16_t pllgfxclkspreadfreq;
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uint8_t uclkspreadenabled;
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uint8_t uclkspreadpercent;
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uint16_t uclkspreadfreq;
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uint8_t socclkspreadenabled;
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uint8_t socclkspreadpercent;
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uint16_t socclkspreadfreq;
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uint8_t acggfxclkspreadenabled;
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uint8_t acggfxclkspreadpercent;
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uint16_t acggfxclkspreadfreq;
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};
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int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
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uint32_t clock_type, uint32_t clock_value,
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struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
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int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
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bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
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struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
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int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
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bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
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uint8_t voltage_type, uint8_t voltage_mode);
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int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_avfs_parameters *param);
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int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_gpio_parameters *param);
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int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_bios_boot_up_values *boot_values);
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int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_smc_dpm_parameters *param);
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int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
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BIOS_CLKID id, uint32_t *frequency);
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#endif
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