mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-21 18:19:03 +07:00
40cff8fca9
The statistics histogram mode was not being explicitly initialized on devices other than the 6390 family. Clearing the statistics then overwrote the default setting, setting the histogram to a reserved mode. Explicitly set the histogram mode for all devices. Change the statistics clear into a read/modify/write, and since it is now more complex, move it into global1.c. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
482 lines
11 KiB
C
482 lines
11 KiB
C
/*
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* Marvell 88E6xxx Switch Global (1) Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/bitfield.h>
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#include "chip.h"
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#include "global1.h"
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int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_read(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_write(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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{
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return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
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}
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/* Offset 0x00: Switch Global Status Register */
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static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
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{
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u16 state;
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int i, err;
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for (i = 0; i < 16; i++) {
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
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if (err)
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return err;
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/* Check the value of the PPUState bits 15:14 */
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state &= MV88E6185_G1_STS_PPU_STATE_MASK;
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if (state != MV88E6185_G1_STS_PPU_STATE_POLLING)
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return 0;
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
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{
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u16 state;
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int i, err;
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for (i = 0; i < 16; ++i) {
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
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if (err)
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return err;
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/* Check the value of the PPUState bits 15:14 */
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state &= MV88E6185_G1_STS_PPU_STATE_MASK;
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if (state == MV88E6185_G1_STS_PPU_STATE_POLLING)
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return 0;
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
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{
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u16 state;
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int i, err;
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for (i = 0; i < 16; ++i) {
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
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if (err)
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return err;
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/* Check the value of the PPUState (or InitState) bit 15 */
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if (state & MV88E6352_G1_STS_PPU_STATE)
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return 0;
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
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{
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const unsigned long timeout = jiffies + 1 * HZ;
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u16 val;
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int err;
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/* Wait up to 1 second for the switch to be ready. The InitReady bit 11
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* is set to a one when all units inside the device (ATU, VTU, etc.)
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* have finished their initialization and are ready to accept frames.
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*/
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while (time_before(jiffies, timeout)) {
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
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if (err)
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return err;
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if (val & MV88E6XXX_G1_STS_INIT_READY)
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break;
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usleep_range(1000, 2000);
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}
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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return 0;
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}
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/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
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* Offset 0x02: Switch MAC Address Register Bytes 2 & 3
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* Offset 0x03: Switch MAC Address Register Bytes 4 & 5
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*/
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int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
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{
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u16 reg;
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int err;
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reg = (addr[0] << 8) | addr[1];
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
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if (err)
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return err;
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reg = (addr[2] << 8) | addr[3];
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
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if (err)
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return err;
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reg = (addr[4] << 8) | addr[5];
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
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if (err)
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return err;
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return 0;
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}
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/* Offset 0x04: Switch Global Control Register */
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int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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/* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
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* the PPU, including re-doing PHY detection and initialization
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*/
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_CTL1_SW_RESET;
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val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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err = mv88e6xxx_g1_wait_init_ready(chip);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_polling(chip);
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}
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int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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/* Set the SWReset bit 15 */
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_CTL1_SW_RESET;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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err = mv88e6xxx_g1_wait_init_ready(chip);
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if (err)
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return err;
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return mv88e6352_g1_wait_ppu_polling(chip);
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}
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int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_polling(chip);
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}
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int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_disabled(chip);
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}
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/* Offset 0x1a: Monitor Control */
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/* Offset 0x1a: Monitor & MGMT Control on some devices */
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int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
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if (err)
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return err;
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reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
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MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
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port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
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}
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/* Older generations also call this the ARP destination. It has been
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* generalized in more modern devices such that more than ARP can
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* egress it
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*/
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int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
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if (err)
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return err;
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reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
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reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
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return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
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}
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static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
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u16 pointer, u8 data)
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{
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u16 reg;
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reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
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return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
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}
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int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 ptr;
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int err;
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
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err = mv88e6390_g1_monitor_write(chip, ptr, port);
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if (err)
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return err;
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
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err = mv88e6390_g1_monitor_write(chip, ptr, port);
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if (err)
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return err;
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return 0;
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}
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int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
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return mv88e6390_g1_monitor_write(chip, ptr, port);
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}
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int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
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{
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u16 ptr;
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int err;
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/* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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return 0;
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}
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/* Offset 0x1c: Global Control 2 */
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int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_CTL2_HIST_RX_TX;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, val);
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return err;
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}
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/* Offset 0x1d: Statistics Operation 2 */
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int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP,
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MV88E6XXX_G1_STATS_OP_BUSY);
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}
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int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
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return err;
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}
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int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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{
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int err;
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/* Snapshot the hardware statistics counters for this port. */
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
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MV88E6XXX_G1_STATS_OP_BUSY |
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MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
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MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
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if (err)
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return err;
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/* Wait for the snapshotting to complete. */
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return mv88e6xxx_g1_stats_wait(chip);
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}
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int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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{
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port = (port + 1) << 5;
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return mv88e6xxx_g1_stats_snapshot(chip, port);
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}
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int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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{
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int err;
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port = (port + 1) << 5;
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/* Snapshot the hardware statistics counters for this port. */
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
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MV88E6XXX_G1_STATS_OP_BUSY |
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MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
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if (err)
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return err;
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/* Wait for the snapshotting to complete. */
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return mv88e6xxx_g1_stats_wait(chip);
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}
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void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
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{
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u32 value;
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u16 reg;
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int err;
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*val = 0;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
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MV88E6XXX_G1_STATS_OP_BUSY |
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MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
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if (err)
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return;
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err = mv88e6xxx_g1_stats_wait(chip);
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if (err)
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return;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
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if (err)
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return;
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value = reg << 16;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
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if (err)
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return;
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*val = value | reg;
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}
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int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
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{
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int err;
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u16 val;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
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if (err)
|
|
return err;
|
|
|
|
/* Wait for the flush to complete. */
|
|
return mv88e6xxx_g1_stats_wait(chip);
|
|
}
|