mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 16:46:43 +07:00
2e1661d267
As synchronous exceptions really only make sense against the current task (otherwise how are you synchronous) remove the task parameter from from force_sig_fault to make it explicit that is what is going on. The two known exceptions that deliver a synchronous exception to a stopped ptraced task have already been changed to force_sig_fault_to_task. The callers have been changed with the following emacs regular expression (with obvious variations on the architectures that take more arguments) to avoid typos: force_sig_fault[(]\([^,]+\)[,]\([^,]+\)[,]\([^,]+\)[,]\W+current[)] -> force_sig_fault(\1,\2,\3) Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
276 lines
5.4 KiB
C
276 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/ptrace.h>
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#include <linux/uaccess.h>
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#include <abi/reg_ops.h>
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#define MTCR_MASK 0xFC00FFE0
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#define MFCR_MASK 0xFC00FFE0
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#define MTCR_DIST 0xC0006420
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#define MFCR_DIST 0xC0006020
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void __init init_fpu(void)
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{
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mtcr("cr<1, 2>", 0);
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}
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/*
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* fpu_libc_helper() is to help libc to excute:
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* - mfcr %a, cr<1, 2>
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* - mfcr %a, cr<2, 2>
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* - mtcr %a, cr<1, 2>
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* - mtcr %a, cr<2, 2>
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*/
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int fpu_libc_helper(struct pt_regs *regs)
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{
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int fault;
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unsigned long instrptr, regx = 0;
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unsigned long index = 0, tmp = 0;
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unsigned long tinstr = 0;
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u16 instr_hi, instr_low;
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instrptr = instruction_pointer(regs);
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if (instrptr & 1)
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return 0;
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fault = __get_user(instr_low, (u16 *)instrptr);
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if (fault)
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return 0;
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fault = __get_user(instr_hi, (u16 *)(instrptr + 2));
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if (fault)
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return 0;
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tinstr = instr_hi | ((unsigned long)instr_low << 16);
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if (((tinstr >> 21) & 0x1F) != 2)
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return 0;
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if ((tinstr & MTCR_MASK) == MTCR_DIST) {
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index = (tinstr >> 16) & 0x1F;
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if (index > 13)
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return 0;
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tmp = tinstr & 0x1F;
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if (tmp > 2)
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return 0;
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regx = *(®s->a0 + index);
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if (tmp == 1)
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mtcr("cr<1, 2>", regx);
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else if (tmp == 2)
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mtcr("cr<2, 2>", regx);
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else
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return 0;
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regs->pc += 4;
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return 1;
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}
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if ((tinstr & MFCR_MASK) == MFCR_DIST) {
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index = tinstr & 0x1F;
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if (index > 13)
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return 0;
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tmp = ((tinstr >> 16) & 0x1F);
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if (tmp > 2)
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return 0;
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if (tmp == 1)
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regx = mfcr("cr<1, 2>");
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else if (tmp == 2)
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regx = mfcr("cr<2, 2>");
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else
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return 0;
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*(®s->a0 + index) = regx;
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regs->pc += 4;
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return 1;
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}
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return 0;
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}
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void fpu_fpe(struct pt_regs *regs)
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{
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int sig, code;
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unsigned int fesr;
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fesr = mfcr("cr<2, 2>");
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sig = SIGFPE;
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code = FPE_FLTUNK;
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if (fesr & FPE_ILLE) {
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sig = SIGILL;
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code = ILL_ILLOPC;
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} else if (fesr & FPE_IDC) {
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sig = SIGILL;
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code = ILL_ILLOPN;
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} else if (fesr & FPE_FEC) {
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sig = SIGFPE;
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if (fesr & FPE_IOC)
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code = FPE_FLTINV;
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else if (fesr & FPE_DZC)
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code = FPE_FLTDIV;
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else if (fesr & FPE_UFC)
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code = FPE_FLTUND;
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else if (fesr & FPE_OFC)
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code = FPE_FLTOVF;
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else if (fesr & FPE_IXC)
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code = FPE_FLTRES;
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}
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force_sig_fault(sig, code, (void __user *)regs->pc);
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}
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#define FMFVR_FPU_REGS(vrx, vry) \
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"fmfvrl %0, "#vrx"\n" \
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"fmfvrh %1, "#vrx"\n" \
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"fmfvrl %2, "#vry"\n" \
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"fmfvrh %3, "#vry"\n"
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#define FMTVR_FPU_REGS(vrx, vry) \
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"fmtvrl "#vrx", %0\n" \
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"fmtvrh "#vrx", %1\n" \
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"fmtvrl "#vry", %2\n" \
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"fmtvrh "#vry", %3\n"
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#define STW_FPU_REGS(a, b, c, d) \
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"stw %0, (%4, "#a")\n" \
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"stw %1, (%4, "#b")\n" \
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"stw %2, (%4, "#c")\n" \
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"stw %3, (%4, "#d")\n"
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#define LDW_FPU_REGS(a, b, c, d) \
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"ldw %0, (%4, "#a")\n" \
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"ldw %1, (%4, "#b")\n" \
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"ldw %2, (%4, "#c")\n" \
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"ldw %3, (%4, "#d")\n"
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void save_to_user_fp(struct user_fp *user_fp)
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{
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unsigned long flg;
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unsigned long tmp1, tmp2;
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unsigned long *fpregs;
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local_irq_save(flg);
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tmp1 = mfcr("cr<1, 2>");
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tmp2 = mfcr("cr<2, 2>");
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user_fp->fcr = tmp1;
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user_fp->fesr = tmp2;
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fpregs = &user_fp->vr[0];
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#ifdef CONFIG_CPU_HAS_FPUV2
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#ifdef CONFIG_CPU_HAS_VDSP
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asm volatile(
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"vstmu.32 vr0-vr3, (%0)\n"
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"vstmu.32 vr4-vr7, (%0)\n"
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"vstmu.32 vr8-vr11, (%0)\n"
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"vstmu.32 vr12-vr15, (%0)\n"
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"fstmu.64 vr16-vr31, (%0)\n"
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: "+a"(fpregs)
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::"memory");
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#else
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asm volatile(
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"fstmu.64 vr0-vr31, (%0)\n"
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: "+a"(fpregs)
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::"memory");
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#endif
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#else
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{
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unsigned long tmp3, tmp4;
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asm volatile(
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FMFVR_FPU_REGS(vr0, vr1)
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STW_FPU_REGS(0, 4, 16, 20)
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FMFVR_FPU_REGS(vr2, vr3)
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STW_FPU_REGS(32, 36, 48, 52)
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FMFVR_FPU_REGS(vr4, vr5)
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STW_FPU_REGS(64, 68, 80, 84)
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FMFVR_FPU_REGS(vr6, vr7)
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STW_FPU_REGS(96, 100, 112, 116)
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"addi %4, 128\n"
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FMFVR_FPU_REGS(vr8, vr9)
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STW_FPU_REGS(0, 4, 16, 20)
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FMFVR_FPU_REGS(vr10, vr11)
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STW_FPU_REGS(32, 36, 48, 52)
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FMFVR_FPU_REGS(vr12, vr13)
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STW_FPU_REGS(64, 68, 80, 84)
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FMFVR_FPU_REGS(vr14, vr15)
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STW_FPU_REGS(96, 100, 112, 116)
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: "=a"(tmp1), "=a"(tmp2), "=a"(tmp3),
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"=a"(tmp4), "+a"(fpregs)
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::"memory");
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}
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#endif
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local_irq_restore(flg);
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}
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void restore_from_user_fp(struct user_fp *user_fp)
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{
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unsigned long flg;
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unsigned long tmp1, tmp2;
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unsigned long *fpregs;
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local_irq_save(flg);
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tmp1 = user_fp->fcr;
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tmp2 = user_fp->fesr;
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mtcr("cr<1, 2>", tmp1);
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mtcr("cr<2, 2>", tmp2);
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fpregs = &user_fp->vr[0];
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#ifdef CONFIG_CPU_HAS_FPUV2
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#ifdef CONFIG_CPU_HAS_VDSP
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asm volatile(
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"vldmu.32 vr0-vr3, (%0)\n"
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"vldmu.32 vr4-vr7, (%0)\n"
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"vldmu.32 vr8-vr11, (%0)\n"
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"vldmu.32 vr12-vr15, (%0)\n"
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"fldmu.64 vr16-vr31, (%0)\n"
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: "+a"(fpregs)
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::"memory");
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#else
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asm volatile(
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"fldmu.64 vr0-vr31, (%0)\n"
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: "+a"(fpregs)
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::"memory");
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#endif
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#else
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{
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unsigned long tmp3, tmp4;
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asm volatile(
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LDW_FPU_REGS(0, 4, 16, 20)
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FMTVR_FPU_REGS(vr0, vr1)
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LDW_FPU_REGS(32, 36, 48, 52)
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FMTVR_FPU_REGS(vr2, vr3)
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LDW_FPU_REGS(64, 68, 80, 84)
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FMTVR_FPU_REGS(vr4, vr5)
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LDW_FPU_REGS(96, 100, 112, 116)
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FMTVR_FPU_REGS(vr6, vr7)
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"addi %4, 128\n"
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LDW_FPU_REGS(0, 4, 16, 20)
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FMTVR_FPU_REGS(vr8, vr9)
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LDW_FPU_REGS(32, 36, 48, 52)
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FMTVR_FPU_REGS(vr10, vr11)
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LDW_FPU_REGS(64, 68, 80, 84)
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FMTVR_FPU_REGS(vr12, vr13)
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LDW_FPU_REGS(96, 100, 112, 116)
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FMTVR_FPU_REGS(vr14, vr15)
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: "=a"(tmp1), "=a"(tmp2), "=a"(tmp3),
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"=a"(tmp4), "+a"(fpregs)
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::"memory");
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}
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#endif
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local_irq_restore(flg);
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}
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