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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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72341af428
We've been accumulating code across the driver that depends on the VBT specific structures and defines. The VBT is an uncontrollable beast. Encourage encapsulation of the VBT data by hiding the structures and defines in a private header only to be included from intel_bios.c. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458125015-7931-7-git-send-email-jani.nikula@intel.com
204 lines
4.6 KiB
C
204 lines
4.6 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/*
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* Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
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* the VBT from the rest of the driver. Add the parsed, clean data to struct
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* intel_vbt_data within struct drm_i915_private.
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*/
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#ifndef _INTEL_BIOS_H_
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#define _INTEL_BIOS_H_
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struct edp_power_seq {
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u16 t1_t3;
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u16 t8;
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u16 t9;
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u16 t10;
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u16 t11_t12;
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} __packed;
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/* MIPI Sequence Block definitions */
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enum mipi_seq {
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MIPI_SEQ_END = 0,
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MIPI_SEQ_ASSERT_RESET,
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MIPI_SEQ_INIT_OTP,
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MIPI_SEQ_DISPLAY_ON,
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MIPI_SEQ_DISPLAY_OFF,
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MIPI_SEQ_DEASSERT_RESET,
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MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
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MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
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MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
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MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */
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MIPI_SEQ_POWER_ON, /* sequence block v3+ */
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MIPI_SEQ_POWER_OFF, /* sequence block v3+ */
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MIPI_SEQ_MAX
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};
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enum mipi_seq_element {
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MIPI_SEQ_ELEM_END = 0,
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MIPI_SEQ_ELEM_SEND_PKT,
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MIPI_SEQ_ELEM_DELAY,
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MIPI_SEQ_ELEM_GPIO,
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MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */
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MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */
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MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */
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MIPI_SEQ_ELEM_MAX
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};
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#define MIPI_DSI_UNDEFINED_PANEL_ID 0
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#define MIPI_DSI_GENERIC_PANEL_ID 1
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struct mipi_config {
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u16 panel_id;
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/* General Params */
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u32 enable_dithering:1;
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u32 rsvd1:1;
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u32 is_bridge:1;
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u32 panel_arch_type:2;
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u32 is_cmd_mode:1;
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#define NON_BURST_SYNC_PULSE 0x1
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#define NON_BURST_SYNC_EVENTS 0x2
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#define BURST_MODE 0x3
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u32 video_transfer_mode:2;
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u32 cabc_supported:1;
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#define PPS_BLC_PMIC 0
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#define PPS_BLC_SOC 1
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u32 pwm_blc:1;
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/* Bit 13:10 */
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#define PIXEL_FORMAT_RGB565 0x1
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#define PIXEL_FORMAT_RGB666 0x2
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#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
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#define PIXEL_FORMAT_RGB888 0x4
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u32 videomode_color_format:4;
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/* Bit 15:14 */
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#define ENABLE_ROTATION_0 0x0
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#define ENABLE_ROTATION_90 0x1
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#define ENABLE_ROTATION_180 0x2
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#define ENABLE_ROTATION_270 0x3
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u32 rotation:2;
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u32 bta_enabled:1;
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u32 rsvd2:15;
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/* 2 byte Port Description */
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#define DUAL_LINK_NOT_SUPPORTED 0
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#define DUAL_LINK_FRONT_BACK 1
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#define DUAL_LINK_PIXEL_ALT 2
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u16 dual_link:2;
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u16 lane_cnt:2;
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u16 pixel_overlap:3;
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u16 rsvd3:9;
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u16 rsvd4;
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u8 rsvd5;
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u32 target_burst_mode_freq;
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u32 dsi_ddr_clk;
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u32 bridge_ref_clk;
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#define BYTE_CLK_SEL_20MHZ 0
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#define BYTE_CLK_SEL_10MHZ 1
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#define BYTE_CLK_SEL_5MHZ 2
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u8 byte_clk_sel:2;
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u8 rsvd6:6;
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/* DPHY Flags */
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u16 dphy_param_valid:1;
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u16 eot_pkt_disabled:1;
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u16 enable_clk_stop:1;
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u16 rsvd7:13;
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u32 hs_tx_timeout;
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u32 lp_rx_timeout;
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u32 turn_around_timeout;
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u32 device_reset_timer;
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u32 master_init_timer;
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u32 dbi_bw_timer;
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u32 lp_byte_clk_val;
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/* 4 byte Dphy Params */
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u32 prepare_cnt:6;
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u32 rsvd8:2;
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u32 clk_zero_cnt:8;
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u32 trail_cnt:5;
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u32 rsvd9:3;
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u32 exit_zero_cnt:6;
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u32 rsvd10:2;
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u32 clk_lane_switch_cnt;
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u32 hl_switch_cnt;
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u32 rsvd11[6];
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/* timings based on dphy spec */
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u8 tclk_miss;
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u8 tclk_post;
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u8 rsvd12;
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u8 tclk_pre;
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u8 tclk_prepare;
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u8 tclk_settle;
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u8 tclk_term_enable;
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u8 tclk_trail;
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u16 tclk_prepare_clkzero;
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u8 rsvd13;
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u8 td_term_enable;
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u8 teot;
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u8 ths_exit;
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u8 ths_prepare;
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u16 ths_prepare_hszero;
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u8 rsvd14;
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u8 ths_settle;
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u8 ths_skip;
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u8 ths_trail;
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u8 tinit;
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u8 tlpx;
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u8 rsvd15[3];
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/* GPIOs */
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u8 panel_enable;
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u8 bl_enable;
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u8 pwm_enable;
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u8 reset_r_n;
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u8 pwr_down_r;
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u8 stdby_r_n;
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} __packed;
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/* all delays have a unit of 100us */
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struct mipi_pps_data {
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u16 panel_on_delay;
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u16 bl_enable_delay;
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u16 bl_disable_delay;
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u16 panel_off_delay;
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u16 panel_power_cycle_delay;
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} __packed;
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#endif /* _INTEL_BIOS_H_ */
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