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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-07 14:56:44 +07:00
a399e3fa79
With a TCLK = 200MHz, the half period of the hardware timer is roughly 10 seconds. Because cnt32_to_63() must be called at least once per half period of the base hardware counter, it is a bit risky to rely solely on scheduling to generate frequent enough calls. Let's use a kernel timer to ensure this. Signed-off-by: Nicolas Pitre <nico@marvell.com>
261 lines
5.9 KiB
C
261 lines
5.9 KiB
C
/*
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* arch/arm/plat-orion/time.c
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*
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* Marvell Orion SoC timer handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Timer 0 is used as free-running clocksource, while timer 1 is
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* used as clock_event_device.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/cnt32_to_63.h>
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#include <linux/timer.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/mach/time.h>
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#include <mach/bridge-regs.h>
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#include <mach/hardware.h>
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/*
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* Number of timer ticks per jiffy.
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*/
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static u32 ticks_per_jiffy;
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/*
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* Timer block registers.
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*/
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#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
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#define TIMER0_EN 0x0001
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#define TIMER0_RELOAD_EN 0x0002
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#define TIMER1_EN 0x0004
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#define TIMER1_RELOAD_EN 0x0008
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#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
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#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
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#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
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#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)
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/*
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* Orion's sched_clock implementation. It has a resolution of
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* at least 7.5ns (133MHz TCLK) and a maximum value of 834 days.
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*
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* Because the hardware timer period is quite short (21 secs if
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* 200MHz TCLK) and because cnt32_to_63() needs to be called at
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* least once per half period to work properly, a kernel timer is
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* set up to ensure this requirement is always met.
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*/
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#define TCLK2NS_SCALE_FACTOR 8
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static unsigned long tclk2ns_scale;
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unsigned long long sched_clock(void)
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{
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unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL));
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return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR;
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}
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static struct timer_list cnt32_to_63_keepwarm_timer;
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static void cnt32_to_63_keepwarm(unsigned long data)
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{
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mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
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(void) sched_clock();
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}
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static void __init setup_sched_clock(unsigned long tclk)
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{
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unsigned long long v;
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unsigned long data;
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v = NSEC_PER_SEC;
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v <<= TCLK2NS_SCALE_FACTOR;
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v += tclk/2;
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do_div(v, tclk);
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/*
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* We want an even value to automatically clear the top bit
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* returned by cnt32_to_63() without an additional run time
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* instruction. So if the LSB is 1 then round it up.
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*/
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if (v & 1)
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v++;
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tclk2ns_scale = v;
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data = (0xffffffffUL / tclk / 2 - 2) * HZ;
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setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data);
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mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
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}
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/*
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* Clocksource handling.
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*/
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static cycle_t orion_clksrc_read(struct clocksource *cs)
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{
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return 0xffffffff - readl(TIMER0_VAL);
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}
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static struct clocksource orion_clksrc = {
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.name = "orion_clocksource",
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.shift = 20,
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.rating = 300,
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.read = orion_clksrc_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Clockevent handling.
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*/
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static int
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orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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unsigned long flags;
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u32 u;
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if (delta == 0)
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return -ETIME;
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local_irq_save(flags);
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/*
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* Clear and enable clockevent timer interrupt.
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*/
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writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
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u = readl(BRIDGE_MASK);
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u |= BRIDGE_INT_TIMER1;
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writel(u, BRIDGE_MASK);
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/*
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* Setup new clockevent timer value.
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*/
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writel(delta, TIMER1_VAL);
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/*
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* Enable the timer.
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*/
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u = readl(TIMER_CTRL);
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u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
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writel(u, TIMER_CTRL);
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local_irq_restore(flags);
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return 0;
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}
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static void
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orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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unsigned long flags;
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u32 u;
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local_irq_save(flags);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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/*
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* Setup timer to fire at 1/HZ intervals.
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*/
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writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
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writel(ticks_per_jiffy - 1, TIMER1_VAL);
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/*
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* Enable timer interrupt.
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*/
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u = readl(BRIDGE_MASK);
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writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
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/*
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* Enable timer.
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*/
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u = readl(TIMER_CTRL);
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writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
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} else {
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/*
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* Disable timer.
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*/
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u = readl(TIMER_CTRL);
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writel(u & ~TIMER1_EN, TIMER_CTRL);
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/*
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* Disable timer interrupt.
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*/
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u = readl(BRIDGE_MASK);
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writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
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/*
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* ACK pending timer interrupt.
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*/
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writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
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}
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local_irq_restore(flags);
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}
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static struct clock_event_device orion_clkevt = {
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.name = "orion_tick",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.rating = 300,
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.set_next_event = orion_clkevt_next_event,
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.set_mode = orion_clkevt_mode,
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};
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static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
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{
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/*
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* ACK timer interrupt and call event handler.
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*/
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writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
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orion_clkevt.event_handler(&orion_clkevt);
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return IRQ_HANDLED;
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}
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static struct irqaction orion_timer_irq = {
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.name = "orion_tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = orion_timer_interrupt
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};
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void __init orion_time_init(unsigned int irq, unsigned int tclk)
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{
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u32 u;
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ticks_per_jiffy = (tclk + HZ/2) / HZ;
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/*
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* Set scale and timer for sched_clock
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*/
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setup_sched_clock(tclk);
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled.)
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*/
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writel(0xffffffff, TIMER0_VAL);
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writel(0xffffffff, TIMER0_RELOAD);
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u = readl(BRIDGE_MASK);
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writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
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u = readl(TIMER_CTRL);
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writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
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orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
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clocksource_register(&orion_clksrc);
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/*
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* Setup clockevent timer (interrupt-driven.)
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*/
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setup_irq(irq, &orion_timer_irq);
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orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
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orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
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orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
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orion_clkevt.cpumask = cpumask_of(0);
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clockevents_register_device(&orion_clkevt);
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}
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