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8e19608e8b
Pass clocksource pointer to the read() callback for clocksources. This allows us to share the callback between multiple instances. [hugh@veritas.com: fix powerpc build of clocksource pass clocksource mods] [akpm@linux-foundation.org: cleanup] Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: John Stultz <johnstul@us.ibm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
216 lines
5.1 KiB
C
216 lines
5.1 KiB
C
/*
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* arch/arm/mach-pxa/time.c
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*
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* PXA clocksource, clockevents, and OST interrupt handlers.
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* Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
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*
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* Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
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* by MontaVista Software, Inc. (Nico, your code rocks!)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/sched.h>
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#include <linux/cnt32_to_63.h>
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#include <asm/div64.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <mach/regs-ost.h>
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/*
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* This is PXA's sched_clock implementation. This has a resolution
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* of at least 308 ns and a maximum value of 208 days.
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*
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* The return value is guaranteed to be monotonic in that range as
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* long as there is always less than 582 seconds between successive
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* calls to sched_clock() which should always be the case in practice.
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*/
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#define OSCR2NS_SCALE_FACTOR 10
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static unsigned long oscr2ns_scale;
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static void __init set_oscr2ns_scale(unsigned long oscr_rate)
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{
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unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
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do_div(v, oscr_rate);
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oscr2ns_scale = v;
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/*
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* We want an even value to automatically clear the top bit
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* returned by cnt32_to_63() without an additional run time
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* instruction. So if the LSB is 1 then round it up.
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*/
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if (oscr2ns_scale & 1)
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oscr2ns_scale++;
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}
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unsigned long long sched_clock(void)
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{
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unsigned long long v = cnt32_to_63(OSCR);
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return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
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}
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#define MIN_OSCR_DELTA 16
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static irqreturn_t
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pxa_ost0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *c = dev_id;
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/* Disarm the compare/match, signal the event. */
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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c->event_handler(c);
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return IRQ_HANDLED;
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}
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static int
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pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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unsigned long flags, next, oscr;
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raw_local_irq_save(flags);
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OIER |= OIER_E0;
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next = OSCR + delta;
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OSMR0 = next;
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oscr = OSCR;
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raw_local_irq_restore(flags);
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return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
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}
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static void
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pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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unsigned long irqflags;
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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raw_local_irq_save(irqflags);
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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raw_local_irq_restore(irqflags);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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/* initializing, released, or preparing for suspend */
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raw_local_irq_save(irqflags);
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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raw_local_irq_restore(irqflags);
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break;
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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}
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}
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static struct clock_event_device ckevt_pxa_osmr0 = {
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.name = "osmr0",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 200,
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.set_next_event = pxa_osmr0_set_next_event,
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.set_mode = pxa_osmr0_set_mode,
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};
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static cycle_t pxa_read_oscr(struct clocksource *cs)
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{
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return OSCR;
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}
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static struct clocksource cksrc_pxa_oscr0 = {
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.name = "oscr0",
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.rating = 200,
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.read = pxa_read_oscr,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static struct irqaction pxa_ost0_irq = {
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.name = "ost0",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = pxa_ost0_interrupt,
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.dev_id = &ckevt_pxa_osmr0,
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};
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static void __init pxa_timer_init(void)
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{
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unsigned long clock_tick_rate = get_clock_tick_rate();
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OIER = 0;
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OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
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set_oscr2ns_scale(clock_tick_rate);
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ckevt_pxa_osmr0.mult =
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div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
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ckevt_pxa_osmr0.max_delta_ns =
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clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
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ckevt_pxa_osmr0.min_delta_ns =
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clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
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ckevt_pxa_osmr0.cpumask = cpumask_of(0);
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cksrc_pxa_oscr0.mult =
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clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
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setup_irq(IRQ_OST0, &pxa_ost0_irq);
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clocksource_register(&cksrc_pxa_oscr0);
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clockevents_register_device(&ckevt_pxa_osmr0);
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}
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#ifdef CONFIG_PM
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static unsigned long osmr[4], oier, oscr;
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static void pxa_timer_suspend(void)
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{
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osmr[0] = OSMR0;
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osmr[1] = OSMR1;
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osmr[2] = OSMR2;
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osmr[3] = OSMR3;
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oier = OIER;
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oscr = OSCR;
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}
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static void pxa_timer_resume(void)
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{
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/*
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* Ensure that we have at least MIN_OSCR_DELTA between match
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* register 0 and the OSCR, to guarantee that we will receive
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* the one-shot timer interrupt. We adjust OSMR0 in preference
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* to OSCR to guarantee that OSCR is monotonically incrementing.
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*/
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if (osmr[0] - oscr < MIN_OSCR_DELTA)
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osmr[0] += MIN_OSCR_DELTA;
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OSMR0 = osmr[0];
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OSMR1 = osmr[1];
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OSMR2 = osmr[2];
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OSMR3 = osmr[3];
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OIER = oier;
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OSCR = oscr;
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}
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#else
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#define pxa_timer_suspend NULL
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#define pxa_timer_resume NULL
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#endif
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struct sys_timer pxa_timer = {
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.init = pxa_timer_init,
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.suspend = pxa_timer_suspend,
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.resume = pxa_timer_resume,
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};
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