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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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35f029e251
Instead of allocating PCI devices I/O port bus addresses from the 000xxxxx I/O port range as intended, due to a bus versus physical address mixup, the Kirkwood PCIe handling code inadvertently allocated I/O port bus addresses from the f20xxxxx address range (which is the physical address range of the PCIe I/O mapping window), but then direct all I/O port accesses to bus addresses 000xxxxx, which would then not be decoded at all. Fix this by setting the base address of the PCIe I/O space struct resource to KIRKWOOD_PCIE_IO_BUS_BASE instead of the incorrect KIRKWOOD_PCIE_IO_PHYS_BASE, and fix up __io() to expect addresses offsetted by the former instead of the latter. (The suggested fix of directing I/O port accesses from the host to bus addresses f20xxxxx instead has the problem that assigning full 32bit I/O port bus addresses (f20xxxxx) doesn't work on all PCI devices, as not all PCI devices implement full 32 bit BAR registers for I/O ports. We should really try to allocate I/O port bus addresses that fit in 16 bits.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> |
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| .. | ||
| include/mach | ||
| addr-map.c | ||
| common.c | ||
| common.h | ||
| cpuidle.c | ||
| db88f6281-bp-setup.c | ||
| irq.c | ||
| Kconfig | ||
| Makefile | ||
| Makefile.boot | ||
| mpp.c | ||
| mpp.h | ||
| mv88f6281gtw_ge-setup.c | ||
| openrd_base-setup.c | ||
| pcie.c | ||
| rd88f6192-nas-setup.c | ||
| rd88f6281-setup.c | ||
| sheevaplug-setup.c | ||
| ts219-setup.c | ||