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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b2edcfc814
Loongson-3 CPU family:
Code-name Brand-name PRId
Loongson-3A R1 Loongson-3A1000 0x6305
Loongson-3A R2 Loongson-3A2000 0x6308
Loongson-3B R1 Loongson-3B1000 0x6306
Loongson-3B R2 Loongson-3B1500 0x6307
Features of R2 revision of Loongson-3A:
- Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache).
- I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is
64 bytes.
- 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way
set-associative).
- Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/
Execute-Inhibit.
[ralf@linux-mips.org: Resolved merge conflicts.]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12751/
Patchwork: https://patchwork.linux-mips.org/patch/13136/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
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* Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
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* Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
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*
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* reference: /proc/cpuinfo,
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* arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
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* arch/mips/kernel/proc.c(show_cpuinfo),
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* loongson2f user manual.
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*/
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#ifndef __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_32fpr 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_4kex 1
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#define cpu_has_64bits 1
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_counter 1
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#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
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#define cpu_has_divec 0
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#define cpu_has_ejtag 0
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#define cpu_has_inclusive_pcaches 1
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#define cpu_has_llsc 1
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#define cpu_has_mcheck 0
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#define cpu_has_mdmx 0
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#define cpu_has_mips16 0
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#define cpu_has_mips3d 0
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#define cpu_has_mipsmt 0
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#define cpu_has_smartmips 0
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#define cpu_has_tlb 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_vce 0
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#define cpu_has_veic 0
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#define cpu_has_vint 0
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#define cpu_has_vtag_icache 0
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#define cpu_has_watch 1
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#define cpu_has_local_ebase 0
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#ifdef CONFIG_CPU_LOONGSON3
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#define cpu_has_wsbh 1
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#define cpu_has_ic_fills_f_dc 1
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#define cpu_hwrena_impl_bits 0xc0000000
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#endif
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#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */
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