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2c73055692
Fix devicetree binding examples for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.
While at it also remove double new lines as a left over from Rob's
commit 4da722ca19 ("dt-bindings: Remove "status" from examples").
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
129 lines
4.8 KiB
Plaintext
129 lines
4.8 KiB
Plaintext
Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
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The Generic Memory Interface bus enables memory transfers between internal and
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external memory. Can be used to attach various high speed devices such as
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synchronous/asynchronous NOR, FPGA, UARTS and more.
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The actual devices are instantiated from the child nodes of a GMI node.
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Required properties:
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- compatible : Should contain one of the following:
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For Tegra20 must contain "nvidia,tegra20-gmi".
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For Tegra30 must contain "nvidia,tegra30-gmi".
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- reg: Should contain GMI controller registers location and length.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must include the following entries: "gmi"
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- resets : Must contain an entry for each entry in reset-names.
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- reset-names : Must include the following entries: "gmi"
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- #address-cells: The number of cells used to represent physical base
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addresses in the GMI address space. Should be 2.
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- #size-cells: The number of cells used to represent the size of an address
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range in the GMI address space. Should be 1.
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- ranges: Must be set up to reflect the memory layout with three integer values
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for each chip-select line in use (only one entry is supported, see below
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comments):
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<cs-number> <offset> <physical address of mapping> <size>
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Note that the GMI controller does not have any internal chip-select address
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decoding, because of that chip-selects either need to be managed via software
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or by employing external chip-select decoding logic.
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If external chip-select logic is used to support multiple devices it is assumed
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that the devices use the same timing and so are probably the same type. It also
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assumes that they can fit in the 256MB address range. In this case only one
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child device is supported which represents the active chip-select line, see
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examples for more insight.
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The chip-select number is decoded from the child nodes second address cell of
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'ranges' property, if 'ranges' property is not present or empty chip-select will
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then be decoded from the first cell of the 'reg' property.
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Optional child cs node properties:
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- nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
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- nvidia,snor-mux-mode: Enable address/data MUX mode.
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- nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
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If omitted it will be asserted with data.
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- nvidia,snor-rdy-active-high: RDY signal is active high
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- nvidia,snor-adv-active-high: ADV signal is active high
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- nvidia,snor-oe-active-high: WE/OE signal is active high
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- nvidia,snor-cs-active-high: CS signal is active high
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Note that there is some special handling for the timing values.
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From Tegra TRM:
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Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
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- nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
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bus. Valid values are 0-15, default is 1
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- nvidia,snor-hold-width: Number of cycles CE stays asserted after the
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de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
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(in case of MASTER Request). Valid values are 0-15, default is 1
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- nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
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Valid values are 0-15, default is 1.
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- nvidia,snor-ce-width: Number of cycles before CE is asserted.
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Valid values are 0-15, default is 4
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- nvidia,snor-we-width: Number of cycles during which WE stays asserted.
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Valid values are 0-15, default is 1
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- nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
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Valid values are 0-255, default is 1
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- nvidia,snor-wait-width: Number of cycles before READY is asserted.
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Valid values are 0-255, default is 3
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Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
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controllers with a simple-bus node since they are all connected to the same
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chip-select (CS4), in this example external address decoding is provided:
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gmi@70009000 {
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compatible = "nvidia,tegra20-gmi";
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reg = <0x70009000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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clocks = <&tegra_car TEGRA20_CLK_NOR>;
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clock-names = "gmi";
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resets = <&tegra_car 42>;
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reset-names = "gmi";
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ranges = <4 0 0xd0000000 0xfffffff>;
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bus@4,0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 4 0 0x40100>;
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nvidia,snor-mux-mode;
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nvidia,snor-adv-active-high;
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can@0 {
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reg = <0 0x100>;
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...
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};
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can@40000 {
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reg = <0x40000 0x100>;
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...
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};
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};
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};
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Example with one SJA1000 CAN controller connected to the GMI bus
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on CS4:
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gmi@70009000 {
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compatible = "nvidia,tegra20-gmi";
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reg = <0x70009000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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clocks = <&tegra_car TEGRA20_CLK_NOR>;
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clock-names = "gmi";
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resets = <&tegra_car 42>;
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reset-names = "gmi";
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ranges = <4 0 0xd0000000 0xfffffff>;
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can@4,0 {
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reg = <4 0 0x100>;
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nvidia,snor-mux-mode;
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nvidia,snor-adv-active-high;
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...
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};
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};
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