mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
4dbbe8dde8
This adds support for U32 filter by using an HW only feature called Flexible RX Parser. This allow us to match any given packet field with a pattern and accept/reject or even route the packet to a specific DMA channel. Right now we only support acception or rejection of frame and we only support simple rules. Though, the Parser has the flexibility of jumping to specific rules as an if condition so complex rules can be established. This is only supported in GMAC5.10+. The following commands can be used to test this code: 1) Setup an ingress qdisk: # tc qdisc add dev eth0 handle ffff: ingress 2) Setup a filter (e.g. filter by IP): # tc filter add dev eth0 parent ffff: protocol ip u32 match ip \ src 192.168.0.3 skip_sw action drop In every tests performed we always used the "skip_sw" flag to make sure only the RX Parser was involved. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Vitor Soares <soares@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Jakub Kicinski <kubakici@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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// Copyright (c) 2017 Synopsys, Inc. and/or its affiliates.
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// stmmac Support for 5.xx Ethernet QoS cores
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#ifndef __DWMAC5_H__
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#define __DWMAC5_H__
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#define MAC_DPP_FSM_INT_STATUS 0x00000140
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#define MAC_AXI_SLV_DPE_ADDR_STATUS 0x00000144
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#define MAC_FSM_CONTROL 0x00000148
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#define PRTYEN BIT(1)
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#define TMOUTEN BIT(0)
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#define MTL_RXP_CONTROL_STATUS 0x00000ca0
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#define RXPI BIT(31)
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#define NPE GENMASK(23, 16)
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#define NVE GENMASK(7, 0)
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#define MTL_RXP_IACC_CTRL_STATUS 0x00000cb0
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#define STARTBUSY BIT(31)
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#define RXPEIEC GENMASK(22, 21)
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#define RXPEIEE BIT(20)
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#define WRRDN BIT(16)
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#define ADDR GENMASK(15, 0)
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#define MTL_RXP_IACC_DATA 0x00000cb4
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#define MTL_ECC_CONTROL 0x00000cc0
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#define TSOEE BIT(4)
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#define MRXPEE BIT(3)
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#define MESTEE BIT(2)
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#define MRXEE BIT(1)
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#define MTXEE BIT(0)
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#define MTL_SAFETY_INT_STATUS 0x00000cc4
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#define MCSIS BIT(31)
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#define MEUIS BIT(1)
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#define MECIS BIT(0)
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#define MTL_ECC_INT_ENABLE 0x00000cc8
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#define RPCEIE BIT(12)
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#define ECEIE BIT(8)
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#define RXCEIE BIT(4)
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#define TXCEIE BIT(0)
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#define MTL_ECC_INT_STATUS 0x00000ccc
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#define MTL_DPP_CONTROL 0x00000ce0
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#define EPSI BIT(2)
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#define OPE BIT(1)
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#define EDPP BIT(0)
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#define DMA_SAFETY_INT_STATUS 0x00001080
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#define MSUIS BIT(29)
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#define MSCIS BIT(28)
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#define DEUIS BIT(1)
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#define DECIS BIT(0)
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#define DMA_ECC_INT_ENABLE 0x00001084
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#define TCEIE BIT(0)
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#define DMA_ECC_INT_STATUS 0x00001088
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int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp);
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int dwmac5_safety_feat_irq_status(struct net_device *ndev,
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void __iomem *ioaddr, unsigned int asp,
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struct stmmac_safety_stats *stats);
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int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
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int index, unsigned long *count, const char **desc);
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int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
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unsigned int count);
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#endif /* __DWMAC5_H__ */
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