mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 12:45:16 +07:00
5ce6c1f353
Atomics present the same issue with locking: release and acquire
variants need to be strengthened to meet the constraints defined
by the Linux-kernel memory consistency model [1].
Atomics present a further issue: implementations of atomics such
as atomic_cmpxchg() and atomic_add_unless() rely on LR/SC pairs,
which do not give full-ordering with .aqrl; for example, current
implementations allow the "lr-sc-aqrl-pair-vs-full-barrier" test
below to end up with the state indicated in the "exists" clause.
In order to "synchronize" LKMM and RISC-V's implementation, this
commit strengthens the implementations of the atomics operations
by replacing .rl and .aq with the use of ("lightweigth") fences,
and by replacing .aqrl LR/SC pairs in sequences such as:
0: lr.w.aqrl %0, %addr
bne %0, %old, 1f
...
sc.w.aqrl %1, %new, %addr
bnez %1, 0b
1:
with sequences of the form:
0: lr.w %0, %addr
bne %0, %old, 1f
...
sc.w.rl %1, %new, %addr /* SC-release */
bnez %1, 0b
fence rw, rw /* "full" fence */
1:
following Daniel's suggestion.
These modifications were validated with simulation of the RISC-V
memory consistency model.
C lr-sc-aqrl-pair-vs-full-barrier
{}
P0(int *x, int *y, atomic_t *u)
{
int r0;
int r1;
WRITE_ONCE(*x, 1);
r0 = atomic_cmpxchg(u, 0, 1);
r1 = READ_ONCE(*y);
}
P1(int *x, int *y, atomic_t *v)
{
int r0;
int r1;
WRITE_ONCE(*y, 1);
r0 = atomic_cmpxchg(v, 0, 1);
r1 = READ_ONCE(*x);
}
exists (u=1 /\ v=1 /\ 0:r1=0 /\ 1:r1=0)
[1] https://marc.info/?l=linux-kernel&m=151930201102853&w=2
https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkAXM
https://marc.info/?l=linux-kernel&m=151633436614259&w=2
Suggested-by: Daniel Lustig <dlustig@nvidia.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <albert@sifive.com>
Cc: Daniel Lustig <dlustig@nvidia.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Jade Alglave <j.alglave@ucl.ac.uk>
Cc: Luc Maranget <luc.maranget@inria.fr>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Akira Yokosawa <akiyks@gmail.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
500 lines
15 KiB
C
500 lines
15 KiB
C
/*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_RISCV_ATOMIC_H
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#define _ASM_RISCV_ATOMIC_H
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#ifdef CONFIG_GENERIC_ATOMIC64
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# include <asm-generic/atomic64.h>
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#else
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# if (__riscv_xlen < 64)
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# error "64-bit atomics require XLEN to be at least 64"
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# endif
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#endif
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#define ATOMIC_INIT(i) { (i) }
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#define __atomic_op_acquire(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
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__asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory"); \
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__ret; \
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})
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#define __atomic_op_release(op, args...) \
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({ \
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__asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); \
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op##_relaxed(args); \
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})
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static __always_inline int atomic_read(const atomic_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void atomic_set(atomic_t *v, int i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC64_INIT(i) { (i) }
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static __always_inline long atomic64_read(const atomic64_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void atomic64_set(atomic64_t *v, long i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#endif
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/*
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* First, the atomic ops that have no ordering constraints and therefor don't
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* have the AQ or RL bits set. These don't return anything, so there's only
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* one version to worry about.
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*/
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#define ATOMIC_OP(op, asm_op, I, asm_type, c_type, prefix) \
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static __always_inline \
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void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
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{ \
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__asm__ __volatile__ ( \
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" amo" #asm_op "." #asm_type " zero, %1, %0" \
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: "+A" (v->counter) \
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: "r" (I) \
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: "memory"); \
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} \
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_OP (op, asm_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_OP (op, asm_op, I, w, int, ) \
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ATOMIC_OP (op, asm_op, I, d, long, 64)
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#endif
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ATOMIC_OPS(add, add, i)
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ATOMIC_OPS(sub, add, -i)
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ATOMIC_OPS(and, and, i)
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ATOMIC_OPS( or, or, i)
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ATOMIC_OPS(xor, xor, i)
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#undef ATOMIC_OP
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#undef ATOMIC_OPS
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/*
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* Atomic ops that have ordered, relaxed, acquire, and release variants.
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* There's two flavors of these: the arithmatic ops have both fetch and return
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* versions, while the logical ops only have fetch versions.
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*/
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#define ATOMIC_FETCH_OP(op, asm_op, I, asm_type, c_type, prefix) \
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static __always_inline \
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c_type atomic##prefix##_fetch_##op##_relaxed(c_type i, \
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atomic##prefix##_t *v) \
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{ \
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register c_type ret; \
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__asm__ __volatile__ ( \
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" amo" #asm_op "." #asm_type " %1, %2, %0" \
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: "+A" (v->counter), "=r" (ret) \
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: "r" (I) \
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: "memory"); \
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return ret; \
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} \
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static __always_inline \
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c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \
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{ \
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register c_type ret; \
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__asm__ __volatile__ ( \
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" amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \
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: "+A" (v->counter), "=r" (ret) \
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: "r" (I) \
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: "memory"); \
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return ret; \
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}
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#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_type, c_type, prefix) \
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static __always_inline \
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c_type atomic##prefix##_##op##_return_relaxed(c_type i, \
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atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##op##_relaxed(i, v) c_op I; \
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} \
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static __always_inline \
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c_type atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##op(i, v) c_op I; \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) \
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ATOMIC_FETCH_OP( op, asm_op, I, d, long, 64) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, d, long, 64)
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#endif
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ATOMIC_OPS(add, add, +, i)
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ATOMIC_OPS(sub, add, +, -i)
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_add_return atomic_add_return
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#define atomic_sub_return atomic_sub_return
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#define atomic_fetch_add atomic_fetch_add
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#define atomic_fetch_sub atomic_fetch_sub
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_add_return atomic64_add_return
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#define atomic64_sub_return atomic64_sub_return
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#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#define atomic64_fetch_add atomic64_fetch_add
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#define atomic64_fetch_sub atomic64_fetch_sub
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#endif
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#undef ATOMIC_OPS
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) \
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ATOMIC_FETCH_OP(op, asm_op, I, d, long, 64)
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#endif
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ATOMIC_OPS(and, and, i)
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ATOMIC_OPS( or, or, i)
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ATOMIC_OPS(xor, xor, i)
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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#define atomic_fetch_and atomic_fetch_and
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#define atomic_fetch_or atomic_fetch_or
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#define atomic_fetch_xor atomic_fetch_xor
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#define atomic64_fetch_and atomic64_fetch_and
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#define atomic64_fetch_or atomic64_fetch_or
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#define atomic64_fetch_xor atomic64_fetch_xor
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#endif
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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/*
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* The extra atomic operations that are constructed from one of the core
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* AMO-based operations above (aside from sub, which is easier to fit above).
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* These are required to perform a full barrier, but they're OK this way
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* because atomic_*_return is also required to perform a full barrier.
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*
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*/
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#define ATOMIC_OP(op, func_op, comp_op, I, c_type, prefix) \
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static __always_inline \
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bool atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_##func_op##_return(i, v) comp_op I; \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, func_op, comp_op, I) \
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ATOMIC_OP(op, func_op, comp_op, I, int, )
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#else
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#define ATOMIC_OPS(op, func_op, comp_op, I) \
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ATOMIC_OP(op, func_op, comp_op, I, int, ) \
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ATOMIC_OP(op, func_op, comp_op, I, long, 64)
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#endif
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ATOMIC_OPS(add_and_test, add, ==, 0)
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ATOMIC_OPS(sub_and_test, sub, ==, 0)
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ATOMIC_OPS(add_negative, add, <, 0)
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#undef ATOMIC_OP
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#undef ATOMIC_OPS
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#define ATOMIC_OP(op, func_op, I, c_type, prefix) \
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static __always_inline \
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void atomic##prefix##_##op(atomic##prefix##_t *v) \
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{ \
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atomic##prefix##_##func_op(I, v); \
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}
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#define ATOMIC_FETCH_OP(op, func_op, I, c_type, prefix) \
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static __always_inline \
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c_type atomic##prefix##_fetch_##op##_relaxed(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##func_op##_relaxed(I, v); \
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} \
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static __always_inline \
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c_type atomic##prefix##_fetch_##op(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##func_op(I, v); \
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}
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#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, c_type, prefix) \
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static __always_inline \
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c_type atomic##prefix##_##op##_return_relaxed(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##op##_relaxed(v) c_op I; \
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} \
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static __always_inline \
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c_type atomic##prefix##_##op##_return(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##op(v) c_op I; \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_OP( op, asm_op, I, int, ) \
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ATOMIC_FETCH_OP( op, asm_op, I, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_OP( op, asm_op, I, int, ) \
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ATOMIC_FETCH_OP( op, asm_op, I, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, int, ) \
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ATOMIC_OP( op, asm_op, I, long, 64) \
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ATOMIC_FETCH_OP( op, asm_op, I, long, 64) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, long, 64)
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#endif
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ATOMIC_OPS(inc, add, +, 1)
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ATOMIC_OPS(dec, add, +, -1)
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#define atomic_inc_return_relaxed atomic_inc_return_relaxed
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#define atomic_dec_return_relaxed atomic_dec_return_relaxed
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#define atomic_inc_return atomic_inc_return
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#define atomic_dec_return atomic_dec_return
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#define atomic_fetch_inc_relaxed atomic_fetch_inc_relaxed
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#define atomic_fetch_dec_relaxed atomic_fetch_dec_relaxed
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#define atomic_fetch_inc atomic_fetch_inc
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#define atomic_fetch_dec atomic_fetch_dec
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define atomic64_inc_return_relaxed atomic64_inc_return_relaxed
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#define atomic64_dec_return_relaxed atomic64_dec_return_relaxed
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#define atomic64_inc_return atomic64_inc_return
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#define atomic64_dec_return atomic64_dec_return
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#define atomic64_fetch_inc_relaxed atomic64_fetch_inc_relaxed
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#define atomic64_fetch_dec_relaxed atomic64_fetch_dec_relaxed
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#define atomic64_fetch_inc atomic64_fetch_inc
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#define atomic64_fetch_dec atomic64_fetch_dec
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#endif
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#undef ATOMIC_OPS
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#undef ATOMIC_OP
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#define ATOMIC_OP(op, func_op, comp_op, I, prefix) \
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static __always_inline \
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bool atomic##prefix##_##op(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_##func_op##_return(v) comp_op I; \
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}
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ATOMIC_OP(inc_and_test, inc, ==, 0, )
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ATOMIC_OP(dec_and_test, dec, ==, 0, )
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#ifndef CONFIG_GENERIC_ATOMIC64
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ATOMIC_OP(inc_and_test, inc, ==, 0, 64)
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ATOMIC_OP(dec_and_test, dec, ==, 0, 64)
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#endif
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#undef ATOMIC_OP
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/* This is required to provide a full barrier on success. */
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static __always_inline int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int prev, rc;
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__asm__ __volatile__ (
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"0: lr.w %[p], %[c]\n"
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" beq %[p], %[u], 1f\n"
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" add %[rc], %[p], %[a]\n"
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" sc.w.rl %[rc], %[rc], %[c]\n"
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" bnez %[rc], 0b\n"
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" fence rw, rw\n"
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"1:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline long __atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long prev, rc;
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__asm__ __volatile__ (
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"0: lr.d %[p], %[c]\n"
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" beq %[p], %[u], 1f\n"
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" add %[rc], %[p], %[a]\n"
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" sc.d.rl %[rc], %[rc], %[c]\n"
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" bnez %[rc], 0b\n"
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" fence rw, rw\n"
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"1:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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static __always_inline int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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return __atomic64_add_unless(v, a, u) != u;
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}
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#endif
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/*
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* The extra atomic operations that are constructed from one of the core
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* LR/SC-based operations above.
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*/
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static __always_inline int atomic_inc_not_zero(atomic_t *v)
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{
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return __atomic_add_unless(v, 1, 0);
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}
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline long atomic64_inc_not_zero(atomic64_t *v)
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{
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return atomic64_add_unless(v, 1, 0);
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}
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#endif
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|
|
|
/*
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* atomic_{cmp,}xchg is required to have exactly the same ordering semantics as
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* {cmp,}xchg and the operations that return, so they need a full barrier.
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*/
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#define ATOMIC_OP(c_t, prefix, size) \
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static __always_inline \
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c_t atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \
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{ \
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return __xchg_relaxed(&(v->counter), n, size); \
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} \
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static __always_inline \
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c_t atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \
|
|
{ \
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|
return __xchg_acquire(&(v->counter), n, size); \
|
|
} \
|
|
static __always_inline \
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|
c_t atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \
|
|
{ \
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|
return __xchg_release(&(v->counter), n, size); \
|
|
} \
|
|
static __always_inline \
|
|
c_t atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \
|
|
{ \
|
|
return __xchg(&(v->counter), n, size); \
|
|
} \
|
|
static __always_inline \
|
|
c_t atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \
|
|
c_t o, c_t n) \
|
|
{ \
|
|
return __cmpxchg_relaxed(&(v->counter), o, n, size); \
|
|
} \
|
|
static __always_inline \
|
|
c_t atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \
|
|
c_t o, c_t n) \
|
|
{ \
|
|
return __cmpxchg_acquire(&(v->counter), o, n, size); \
|
|
} \
|
|
static __always_inline \
|
|
c_t atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \
|
|
c_t o, c_t n) \
|
|
{ \
|
|
return __cmpxchg_release(&(v->counter), o, n, size); \
|
|
} \
|
|
static __always_inline \
|
|
c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \
|
|
{ \
|
|
return __cmpxchg(&(v->counter), o, n, size); \
|
|
}
|
|
|
|
#ifdef CONFIG_GENERIC_ATOMIC64
|
|
#define ATOMIC_OPS() \
|
|
ATOMIC_OP( int, , 4)
|
|
#else
|
|
#define ATOMIC_OPS() \
|
|
ATOMIC_OP( int, , 4) \
|
|
ATOMIC_OP(long, 64, 8)
|
|
#endif
|
|
|
|
ATOMIC_OPS()
|
|
|
|
#undef ATOMIC_OPS
|
|
#undef ATOMIC_OP
|
|
|
|
static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset)
|
|
{
|
|
int prev, rc;
|
|
|
|
__asm__ __volatile__ (
|
|
"0: lr.w %[p], %[c]\n"
|
|
" sub %[rc], %[p], %[o]\n"
|
|
" bltz %[rc], 1f\n"
|
|
" sc.w.rl %[rc], %[rc], %[c]\n"
|
|
" bnez %[rc], 0b\n"
|
|
" fence rw, rw\n"
|
|
"1:\n"
|
|
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
|
|
: [o]"r" (offset)
|
|
: "memory");
|
|
return prev - offset;
|
|
}
|
|
|
|
#define atomic_dec_if_positive(v) atomic_sub_if_positive(v, 1)
|
|
|
|
#ifndef CONFIG_GENERIC_ATOMIC64
|
|
static __always_inline long atomic64_sub_if_positive(atomic64_t *v, int offset)
|
|
{
|
|
long prev, rc;
|
|
|
|
__asm__ __volatile__ (
|
|
"0: lr.d %[p], %[c]\n"
|
|
" sub %[rc], %[p], %[o]\n"
|
|
" bltz %[rc], 1f\n"
|
|
" sc.d.rl %[rc], %[rc], %[c]\n"
|
|
" bnez %[rc], 0b\n"
|
|
" fence rw, rw\n"
|
|
"1:\n"
|
|
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
|
|
: [o]"r" (offset)
|
|
: "memory");
|
|
return prev - offset;
|
|
}
|
|
|
|
#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(v, 1)
|
|
#endif
|
|
|
|
#endif /* _ASM_RISCV_ATOMIC_H */
|