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AVX512_4VNNIW - Vector instructions for deep learning enhanced word variable precision. AVX512_4FMAPS - Vector instructions for deep learning floating-point single precision. These new instructions are to be used in future Intel Xeon & Xeon Phi processors. The bits 2&3 of CPUID[level:0x07, EDX] inform that new instructions are supported by a processor. The spec can be found in the Intel Software Developer Manual (SDM) or in the Instruction Set Extensions Programming Reference (ISE). Define new feature flags to enumerate the new instructions in /proc/cpuinfo accordingly to CPUID bits and add the required xsave extensions which are required for proper operation. Signed-off-by: Piotr Luc <piotr.luc@intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/20161018150111.29926-1-piotr.luc@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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| .. | ||
| alpha/include | ||
| arc/include/uapi/asm | ||
| arm/include | ||
| arm64/include | ||
| frv/include/uapi/asm | ||
| h8300/include | ||
| hexagon/include/uapi/asm | ||
| ia64/include | ||
| m32r/include/uapi/asm | ||
| microblaze/include/uapi/asm | ||
| mips/include | ||
| mn10300/include/uapi/asm | ||
| parisc/include/uapi/asm | ||
| powerpc/include | ||
| s390/include | ||
| score/include/uapi/asm | ||
| sh/include | ||
| sparc/include | ||
| tile/include | ||
| x86 | ||
| xtensa/include | ||